In this paper a low power and low area array multiplier with carry save adder is proposed. The proposed adder eliminates the final addition stage of the multiplier than the conventional parallel array multiplier. The conventional and proposed multiplier both are synthesized with 16-T full adder. Among Transmission Gate, Transmission Function Adder, 14-T, 16-T full adder shows energy efficiency....

Processor speed largely governed by the multiplier architectures. It is desired to have faster ALU with lower power consumption for portable applications to have good battery life. Hence, there is need to address different multiplier architectures. In this paper, the analysis of 4-bit multiplier using a Vedic Mathematics (Urdhva Tiryagbhyam sutra) and conventional multiplier with two different ...

The Multiplier Hopf Group Coalgebra was introduced by Hegazi in 2002 [] as a generalization of Hope group caolgebra, introduced by Turaev in 2000 [], in the non-unital case. We prove that the concepts introduced by A.Van Daele in constructing multiplier Hopf algebra [3] can be adapted to serve again in our construction. A multiplier Hopf group coalgebra is a family of algebras A = {A α } α∈π , ...

In this paper, we propose a pipeline scheme for efficient realization of a complex multiplier using distributed arithmetic. The pipelined multiplier consists of one conventional multiplier that is multiplexed and some small additional circuitry on the boundary. The proposed scheme reduces the chip area as well as the interconnections by nearly half compared to a conventional complex multiplier....

Abstract. In this paper we are concerned with a multiplier ω(n) of the Progressive means, and convex maps of the unit disc. With this concern we would have brought up in a rather unified approach the results of G. Pólya and I. J. Schoenberg in [7], T. Başgöze, J. L. Frank, and F. R. Keogh in [3], and Ziad S. Ali in [1]. More theorems on the properties of the multiplier ω(n) are given, and a key...

Design of a high performance and high-density multiplier is presented. This multiplier is constructed by using the Wallace tree structure with pipelining. A fast carry select adder is used for the final two-operand adder. It is shown that the time delay for the entire multiplier is O(log(n)). The design is particularly carried out for a 32-bit multiplier with two sections of pipelining, to bala...

We present a new low-complexity bit-parallel canonical basis multiplier for the field GF(2 m ) generated by an all-onepolynomial. The proposed canonical basis multiplier requires m 2 1 XOR gates and m 2 AND gates. We also extend this canonical basis multiplier to obtain a new bit-parallel normal basis multiplier.

In the recent year growth of the portable electronics is forcing the designers to optimize the existing design for better performance. Multiplication is the most commonly used arithmetic operation in various applications like, DSP processor, math processor and in various scientific applications. In this paper a low power bypassing -based multiplier design is present, in which reduction in power...

Multipliers play a vital role in many cryptographic applications like elliptic curve cryptography, RSA and other algorithms. The direct truncation of least significant part of the product leads to large error in the resultant product when fixed width output is the requirement. This paper proposes a truncation error minimizing logic which greatly reduces truncation error. Truncation error minimi...