Partitioning is a critical area of VLSI CAD. In order to build complex digital logic circuits it is often essential to sub-divide a circuit into smaller parts.Circuit partitioning plays an important role in physical design automation of very large scale integration(VLSI)chips.In VLSI.In VLSI circuit partitioning the problem of obtaining minimum cut is of prime importance.To enhance other criter...

As interests in implantable devices and bio-electrical systems grow, intelligent embedded systems become important for extracting useful information from continuous-valued, noisy and drifting biomedical signals at sensory interfaces. Probabilistic generative models utilise stochasticity to represent the natural variability of real data, and therefore suggest a potential approach to this applica...

Field-effect transistors based on two-dimensional (2D) materials have the potential to be used in very large-scale integration (VLSI) technology, but whether they can at front end of line or back through monolithic heterogeneous remains determined. To achieve this, multiple challenges must overcome, including reducing contact resistance, developing stable and controllable doping schemes, advanc...

This paper considers the rate optimal VLSI design of a recursive data ow graph (DFG). Previous research on rate optimal scheduling is not directly applicable to VLSI design. We propose a technique that inserts bu er registers to allow overlapped rate optimal implementation of VLSI. We illustrate that nonoverlapped schedules can be implemented by a simpler control path but with a larger unfoldin...

In this new technology era, circuit partitioning is a fundamental problem in very large-scale integration (VLSI) physical design automation. In this brief, we present a new interconnection oriented clustering algorithm for combinational VLSI circuit partitioning. The proposed clustering method focuses on capturing clusters in a circuit, i. e. , the groups of cells that are highly interconnected...

<span lang="EN-US">Growing endless demand for digital processing technology, to perform high speed computations with low power utilization and minimum propagation delay, the metal-oxide-semiconductor (MOS) technology is implemented in areas of very large scale integrated (VLSI) circuit technology. But MOS facing challenges linear scaling transistors different channel modelling present day...

VLSI logic simulation is an application area in which execution time improvements can have direct economic benefits. Here, we investigate the use of parallel simulation techniques to improve the performance of VLSI logic simulation, including the often neglected issue of sensitivity to variations in the simulation workload. Performance predictions are presented for the use of speculative comput...

Until recently, VLSI designers rarely considered yield issues when selecting a floorplan for a newly designed chip. This paper demonstrates that for large area VLSI chips, especially those that incorporate some fault tolerance, changes in the floorplan can affect the projected yield. We study several general floorplan structures, make some specific recommendations, and apply them to actual VLSI...

The Computer Systems Laboratory has been involved in a VLSI research program for one and a half years. The major areas under investigation have included: analysis and synthesis design aids, applications of VLSI to computer graphics, !he design of a personal workstation, special purpose chip design, VLSI computer architectures, and hardware specification and verification. Progress on these resea...