In this letter, an area-efficient FFT processor is proposed for MIMO-OFDM based SDR systems. The proposed FFT processor can support variable lengths of 64, 128, 256, 512, 1024, 1536 and 2048. By reducing the required number of non-trivial multipliers with a mixed-radix algorithm, the complexity of the proposed FFT processor is dramatically decreased. The proposed FFT processor was designed in a...

This paper presents a high-throughput lowcomplexity 512-point eight-parallel mixed-radix multipath delay feedback (MDF) fast Fourier transform (FFT) processor architecture for orthogonal frequency division multiplexing (OFDM) applications. To decrease the number of twiddle factor (TF) multiplications, a mixed-radix 2/2 FFT algorithm is adopted. Moreover, a dual-path shared canonical signed digi...

FFT algorithms optimized to achieve high performance on a speciic parallel computer architecture are not portable without a reduction in performance. The main objective of this paper is to present a portable FFT algorithm that runs eeciently on diierent parallel computer systems. This goal can only be achieved if the algorithm is able to adapt itself to the computer system it runs on. The struc...

In our previous study, we proposed a post FFT frequency domain adaptive antenna array (FD-AAA) algorithm for the uplink detection in the broadband single-carrier multiple access system. In the post-FFT algorithm, the AAA weights on different frequencies are calculated respectively. In this study, we will compare the performance of the proposed algorithm with the pre-FFT type algorithm where the...

Without doubt, the fast Fourier transform (FFT) belongs to the algorithms with large impact on science and engineering. By appropriate approximations, this scheme has been generalized for arbitrary spatial sampling points. This so called nonequispaced FFT is the core of the sequential NFFT3 library and we discuss its computational costs in detail. On the other hand, programmable graphics proces...

This paper presents a single-chip 128point FFT processor based on the cached-memory architecture (CMA) with the resource Mixed Radix 4-2 computation element. The 4-2-stage CMA, including a pair of single-port SRAMs, is introduced to increase the execution time of the 2dimensional FFT’s. Using the above techniques, we have designed an FFT processor core which integrates 5,52,000 transistors with...

Spectral analysis is an important area in signal processing with wide range of application. A low complexity algorithm to compute the power spectral density (PSD) using the Welch method is presented in this paper. The Welch algorithm computes spectral power at the cost of high computational complexity. In order to reduce the complexity and hardware utilization pipelining FFT approach is used. I...

This paper presents an Orthogonal Frequency Division Multiplexing (OFDM) transceiver that makes use of a low power Fast Fourier Transform (FFT) along with a Least Mean Square (LMS) filter. The folded FFT is developed via folding transformation and register minimization techniques with real values as inputs which leads to reduction in hardware complexity by exploiting the redundancy present in c...

ABSTARCT: In this paper, an optimized efficient VLSI architecture of a pipeline Fast Fourier transform (FFT) processor capable of producing the reverse output order sequence is presented. Paper presents Radix-2 multipath delay architecture for FFT calculation. The implementation of FFT in hardware is very critical because for calculation of FFT number of butterfly operations i.e. number of mult...

In this paper a Split Radix FFT without the use of multiplier is designed. All the complex multiplications are done by using Distributed Arithmetic (DA) technique. For faster calculation parallel prefix adder is used. Basically high radix algorithms are developed for efficient calculation of FFT. These algorithms reduces overall arithmetic operations in FFT, but increases the number of operatio...