Electrical Engineering (ABSTRACT) Hardware description languages (HDLs) such as VHDL have made it possible for circuit and board designs to be done without resorting to paper, allowing computers to manage the design database and automate the translation between various representations of the system. Although VHDL modeling can provide a bonanza of benefits, VHDL models must be used effectively t...

Simulations and prototyping have been a very important part of the electronics industry since a very long time. In recent years, FPGA‘s have become increasingly important and have found their way into all kind of digital system design This paper presents a novel, easy and efficient approach of implementation and verification of VHDL code using Simulink and then to regenerate the optimized VHDL ...

The study of fat body receptors (e.g., VHDL receptor) in Lepidoptera has been irksome due to the fact that isolation and purification of these proteins are difficult and resulted in extremely low yields. A rapid and efficient method is presented for the purification of Helicoverpa zea VHDL receptor by the use of VHDL-biotin ligand complexed to streptavidin coated magnetic beads. The technique c...

This paper discusses the use of fault models for the diagnosis of hardware designs written in the VHDL hardware description language. VHDL designs are concurrent programs consisting of hundreds of thousands of lines of source code, whose testing and debugging is a very time-consuming process. Building on an abstract representation that allows the search for errors in even the largest VHDL progr...

This paper describes the use of model-based diagnosis for locating bugs in hardware designs. We restrict our view to hardware designs written in a subset of the commonly used hardware description language VHDL. This subset includes all synthesizeable (register transfer level) programs. This are programs which can be automatically converted into a gate level description without changing their be...

The main purpose of this study is to yield the gains obtained by the developers with the usage of Viterbi algorithm. Research mainly centers on the grandness of Viterbi algorithm in the practical applications with the VHDL code. Research not only helps the students related to the communications but it also helps the people who are in the field of decoders as it is one of the efficient method fo...

This paper reviews the requirements on a language for modeling behaviour and structure at the system level, and considers possible approaches to extending VHDL to meet these requirements. Modeling issues that obtain in a system-level design language are identified, including abstraction of data, concurrency, communication and timing, and design refinement. Some system-level design languages and...

We present a new approach to speeding up VHDL simulation. In this approach, the simulation code is generated with routines for unused VHDL features stripped oo. The VHDL simulator optimized in this way runs faster when the design is described mostly with simple constructs and expressions. We prepare multiple functions for each task in the simulation process. Each function is pre-optimized for e...

Mixed-Signal extensions to VHDL and SystemC languages have been developed in order to provide a unifying environment for the modeling and verification of AMS designs at different levels of abstraction. In this paper, we model the behavior of a set of benchmark designs in VHDL-AMS and SystemC-AMS and compare the simulation run-time with the low level HSPICE simulation run-time. The various exper...