To store anything in the form of bits, we need memory. Memory can be formed with the integration of large number of basic storing element called cell. SRAM cell is one of the basic storingelement. There is further scope of improving the performance of SRAM cell.This paper provides a review of various proposed schemes used to improve the stability of SRAM cell and to reduce its area and power co...

Ternary Content Addressable memory is a type of memory that allows the memory to be searched by content rather than by address. It performs high speed lookup operations within a single clock cycle. But when compared to RAM technology the conventional TCAM circuitry has certain limitations such as low access time, low storage capacity, circuit complexity and high cost. So we can use the benefits...

Purpose: CMOS devices are scaling down to nano ranges resulting in increased process variations and short channel effects which not only affect the reliability of the device but also performance expectations. The SRAM design uses the smallest transistors possible and is also susceptible to reliability issues and process variations, making it an ideal benchmark circuit to compare the two technol...

Computing-in-memory (CIM) is a promising approach to reduce latency and improve the energy efficiency of multiply-and-accumulate (MAC) operation under memory wall constraint for artificial intelligence (AI) edge processors. This paper proposes an focusing on scalable CIM designs using new ten-transistor (10T) static random access (SRAM) bit-cell. Using proposed 10T SRAM bit-cell, we present two...

One of the major reliability concerns in nano-scale VLSI design is the time dependent Negative Bias Temperature Instability (NBTI) degradation. Due to the higher operating temperature and increasing vertical oxide field, threshold voltage (Vt) of PMOS transistors can increase with time under NBTI. In this paper, we examine the impact of NBTI degradation in memory elements of digital circuits, f...

Semiconductor manufacturing process scaling increases leakage and transistor variations, both of which are problematic for static random access memory (SRAM). Since SRAM is a critical component in modern CMOS integrated circuits, novel approaches to addressing these problems are needed. Here, six and seven transistor SRAM cells are presented that do not suffer from reduced stability when read. ...

Power dissipation is one of the major concerns of Very Large Scale Integration (VLSI) circuit designs. Leakage power is becoming the dominant power component in deep submicron technology. In this work a new 9T adiabatic SRAM is presented. The elementary cell structure of adiabatic SRAM consists of two high load resistors which are constructed of PMOS, a cross-coupled NMOS pair, NMOS switch whic...

The occupancy of caches has tended to be dominated by the logic bit value ‘0’ approximately 75% of the time. Periodic bit flipping can reduce this to 50%. Combining cache power saving strategies with bit flipping can lower the effective logic bit value ‘0’ occupancy ratios even further. We investigate how Negative Bias Temperature Instability (NBTI) affects different power saving cache strategi...

SRAM cell read stability and write-ability are major concerns in CMOS technologies, due to the progressive increase in VDD and transistor scaling. In this paper, we studied and comparedthe performance of 7TN (with NMOS access transistor), 7TP (with PMOS access transistor) andconventional 6T structure.SRAM cells have been simulated in SPICE with 0.35 μm technology. The techniques that provide th...

The majority of space taken in an integrated circuit is the memory. SRAM design consists of key considerations, such as increased speed, low power and reduced layout area. A cell which is functional at the nominal supply voltage, can fail at a lower voltage. From a system perspective this leads to a higher bit-error rate with voltage scaling and limits the opportunity for power saving. While th...