Актуальність. Аналіз даних, зокрема їх класифікація) часто виконується за допомогою методів машинного навчання. Часто задіяні алгоритми потрібні мати справу з великими наборами що призводить до тривалого часу виконання. Таким чином, актуальним є дослідження апаратних прискорювачів, на базі програмованої вентильної матриці (FPGA) для покращення продуктивності. FPGA перспективним рішенням апаратн...

In this paper we present a solution where only one FPGA is needed in a host coupled system, in which the FPGA can be reconfigured by a user application during run-time without loosing the host link connection. A hardware infrastructure on the FPGA and the software framework ACCFS (ACCelerator File System) on the host system is provided to the user which allow easy handling of reconfiguration an...

This paper proposes a kind of project which is about FPGA (the Field Programmable Gate Array, FPGA) hardware implementation scheme for PID AQM algorithm. According to the analyses of the relatively mature discrete PID algorithm, we realized PID algorithm by using the combination of LPM (Library of Parameter Modules) macro module and Verilog code in FPGA. In this article, we write the program of...

In this paper, an efficient design scheme for implementation of the Proportional-IntegralDerivative (PID) controller using Field Programmable Gate Array (FPGA) technology is presented. It is efficient scheme in the sense dynamic power system, effective cost over other digital implementation techniques and etc. The VHDL (VHSIC Hardware Description Language; VHSIC: very-high-speed-integrated circ...

In reconfigurable computing systems, are evolving rapidly, due to their flexibility and high performance. In this paper, we focus on communication cost between partitions in order to develop an algorithm to solve temporal partitioning problems for reconfigurable architecture. In fact, this algorithm optimizes the transfer of data required between design partitions. The proposed algorithm was te...

While FPGA accelerator boards and their respective high-level design tools are maturing, there is still a lack of multi-FPGA applications, libraries, not least, benchmarks reference implementations towards sustained HPC usage these devices. As in the early days GPUs HPC, for workloads that can reasonably be decoupled into loosely coupled working sets, multi-accelerator support achieved by using...