Two embedded processor based fault injection case studies are presented which are applicable to Field Programmable Gate Arrays (FPGAs) and FPGA cores in configurable System-on-Chip (SoC) implementations. The case studies include embedded hard core and soft core processors which manipulate configuration memory bits to emulate physical and transient faults in the FPGA core including shorts and op...

Systems designed with FPGAs benefit from significant improvements over ASICS, such as rapid-process technology scaling and design innovation, which permit the use of FPGAs in high-availability, high-reliability, and safety-critical systems. However, along with technology scaling come other effects such as increased susceptibility to soft errors that previously could be ignored. These soft error...

At the system level, SEUs in processors are controlled by fault-tolerance techniques such as replication and voting, watchdog processors, and tagged data schemes [13,16,30]. SEUs in memory subsystems are controlled by use of error control codes (ECCs) [4,17,21] and a process called scrubbing. The scrubbing process periodically reads each word in the memory. If the number of faulty digits in a w...

This paper investigates the behavior of a SEU tolerant 8051-like micro-controller protected by single error correction Hamming Code in the presence of multiple upsets. Single event upsets (SEUs) and multiple bit upsets (MBUs) were analyzed, since they are more likely to occur in nano-metric technologies under high-energy heavy-ions. Upsets were randomly injected in all sensitive parts of the de...

SRAM-based reconfigurable programmable logic is widely used in commercial applications and occasionally used in space flight applications because of its susceptibility to singleevent upset (SEU). Upset detection and mitigation schemes have been tested on the Xilinx Virtex II X-2V1000 in heavy-ion and proton irradiation to control the accumulation of SEUs and to mitigate their effects on the int...

Fault testing of resistive manufacturing defects is done on a recently developed single event upset immune logic family. Resistive ranges and delay times are compared with those of traditional CMOS logic. Reaction of the logic to these defects is observed for a NOR gate and an evaluation of its ability to cope with them is determined.

Nanometer CMOS VLSI circuits are highly sensitive to soft errors, also known as single-event upsets (SEU) that induce current pulses at random times and at random locations in a digital circuit. Environmental causes of SEU include cosmic radiation and high-energy particles. Our neutron induced soft error rate (SER) estimation method propagates single event transient (SET) pulses through the aff...

A series of experiments were carried out at the Radiation Effects Facility (RADEF) [1] in the Accelerator laboratory of the University of Jyväskylä. Experiments consisted in irradiating the memory arrays in vacuum with a variety of heavy ions. The effect of Linear Energy Transfer (LET) of incoming ion and component operating mode (static/active) [2] on the component failure mode (SEU/MBU/SEFI) ...