The Lightweight Secure Physically Unclonable Function (LSPUF) was proposed as a secure composition of Arbiter PUFs with additional XOR based input and output networks. But later, researchers proposed a Machine Learning (ML) based modeling attack on x-XOR LSPUF, and they also empirically showed that pure ML based modeling is not computationally scalable if the parameter x of x-XOR LSPUF is large...

Yao’s garbled-circuit approach enables constant-round secure two-party computation for any boolean circuit. In Yao’s original construction, each gate in the circuit requires the parties to perform a constant number of encryptions/decryptions, and to send/receive a constant number of ciphertexts. Kolesnikov and Schneider (ICALP 2008) proposed an improvement that allows XOR gates in the circuit t...

By selecting the largest possible value of k ∈ (n/2, 2n/3], we further reduce the AND and XOR gate complexities of the CRT-based hybrid parallel GF (2) polynomial basis multipliers for the irreducible trinomial f = u + u + 1 over GF (2): they are always less than those of the current fastest parallel multipliers – quadratic multipliers, i.e., n AND gates and n− 1 XOR gates. Our experimental res...

Synthetic biology is an emerging scientific field that utilizes biological principles to predictably engineer organisms to perform useful functions. In addition to holding great potential for solving real world problems, this multidisciplinary field offers valuable insight into specific areas where our understanding of biology is incomplete or wrong. Before complex systems can be engineered, it...

In this paper, we present a new synthesis feature namely, “Xor matching”, and the foldback product term synthesis for Complex Programmable Logic Devices (CPLD) architecture that is based on PAL-like macrocells. Our goal is to use the Xor gate and the foldback terms, (or shareable expander − Altera equivalent terminology [17]), available in each macrocell for minimizing the number of macrocells ...

Motivations of CMOS technology scaling are higher speed of operation, benefit of integration density and lower power dissipation. CMOS technology has crossed many hurdles over the past four decades. The aggressive technology scaling is causing device parameter variations, which is more severe than earlier. This paper carries out variability analysis of various popular exclusive-OR circuits at t...

We have developed a new microelectromechanical logic device using the MEMS (Micro Electro Mechanical Systems) technology. This device consists simply of a single cantilever and two driving electrodes with two contact pads for electrostatic operation. Both exclusive NOR (XNOR) and exclusive OR (XOR) logic devices have been realized using this simple construction.

At EUROCRYPT 2015, Zahur et al. argued that all linear, and thus, efficient, garbling schemes need at least two k-bit elements to garble an AND gate with security parameter k. We show how to circumvent this lower bound, and propose an efficient garbling scheme which requires less than two k-bit elements per AND gate for most circuit layouts. Our construction slightly deviates from the linear ga...

A new GF(2) redundant representation is presented. Squaring in the representation is almost cost-free. Based on the representation, two multipliers are proposed. The XOR gate complexity of the first multiplier is lower than a recently proposed normal basis multiplier when CN (the complexity of the basis) is larger than 3n-1. Index Terms Finite field, normal basis, redundant set, Massey-Omura mu...