VLSI architecture for 1-D lifting DWT is proposed in this paper. All resolution levels are folded to same high-pass and low-pass filters. Hardware utilisation of the proposed architecture is very high. Compared with other known architectures, the proposed architecture requires less complex control circuit.

This paper describes the architecture of a new pure digital frequency synthesizer based on pulse generators, counters and a register. The technique described here is much simpler than other methods. The synthesizer presented is suitable for the design of VLSI architectures or for programmable large-scale integration circuits.

SUMMARY In this thesis we study the possibility of using logic replication in order to improve timing performance in VLSI design. In particular, we restrict our analysis to FPGA architectures. We describe an algorithm for post-placement timing optimization that exploits the additional freedom degree of logic duplication.

We investigate three approaches to VLSI implementation of wavelet lters. The direct form structure, the lattice form structure, and an algebraic structure are used to derive diierent architectures for wavelet lters. The algebraic structure exploits conjugacy properties in number elds. All approaches are explained in detail for the Daubechies 4-tab lters. We outline the philosophy of a design me...

M arkovian approaches to early vision processes need a huge amount of computing power. These algorithms can usually be implemented on parallel computing structures. Herein, we show that the Markovian labeling approach can be implemented in fully parallel cellular network architectures, using simple functions and data representations. This makes possible to implement our model in parallel imagin...

Systolic architectures for inversion in Galois eld (GF (2)) are presented. The proposed inversion algorithm is a counter-free extended Euclidean algorithm, which results in simple circuit implementation for GF inversion. Additionally, the bit-parallel implementation proposed is shown to be C-testable. Testability and modularity make it suited to VLSI implementation.

This paper describes a new mesh-connected SIMD architecture, called a Sliding Memory Plane (SIiM) Array Processor. On SIiM, the inter-processing element (inter-PE) communication, using the sliding memory plane, and the data input/output (I/O), using two U 0 planes, can occur without interrupting the PE’s, which greatly diminishes the communication and I/O overhead. SliM is unique in its ability...

In the companion paper, we addressed the low-power DCT/IDCT VLSI architectures of linear complexity increase based on the multirate approach. In this paper, we will discuss other aspects of the low-power design. Firstly, we consider the design of low-power architectures that can lower the power consumption at only O(log M) increase in hardware complexity. Next, we will extend the low-power DCT ...

In this article, we present the BinDCT algorithm, a fast approximation of the Discrete Cosine Transform, and its efficient VLSI architectures for hardware implementations. The design objective is to meet the real-time constrain in embedded systems. Two VLSI architectures are proposed. The first architecture is targeted for low complexity applications such as videophones, digital cameras, and di...

The main contribution of this work is to propose two application-specific bus architectures for computing the p r e f i sums of a binary sequence. Our architectures feature the following characteristics: (1) all broadcasts occur on buses of length I5 or 63; ( 2 ) we use a new technique t h a ~ we call shift switching which allows switches to cyclically permute an incoming signul, dramatically i...