Functional verification is a critical and timeconsuming task in complex VLSI designs. There are two main challenges to functional verification: the first is to insure that the input stimulus can control the function spots inside the design and the second is to insure that the errors can be observed at the design output(s). Over the years, assertion-based verification techniques have been playin...

Model checking and runtime verification are pillars of formal verification but for the most part are used independently. In this position paper we argue that the formal verification community would be well-served by developing theory, algorithms, implementations, and applications that combine model checking and runtime verification into a single, seamless technology. This technology would allow...

Verification is a major bottleneck in today’s design flow. As the functional verification is time consuming, it is constantly being reconsidered. We propose a new verification framework based on the SystemC verification standard that uses MATLAB and Simulink to accelerate testbench development. Our major contributions are first a cosimulation interface between SystemC and MATLAB and Simulink, a...

Software verification tools have become a lot more powerful in recent years. Even verification of large, complex systems is feasible, as demonstrated in the L4.verified and Verisoft XT projects. Still, functional verification of large software systems is rare – for reasons beyond the large scale of verification effort needed due to the size alone. In this paper we report on lessons learned for ...

Formal specification and verification is required for high security level DBMS in the top level specification design. The specification and verification towards SQL operations is important especially. In this paper, we propose a novel approach to solve the specification and verification issues towards SQL operations. Firstly, we formally define the SQL operations in FTLS; then, we give the defi...

Processor verification is a time consuming task and with processor complexity increasing by the day, managing the complete verification process successfully has become a major challenge. Besides, a small bug in the final product may ruin all the efforts and could prove as a critical setback. This problem has resulted in verification methodologies, like formal verification, gaining considerable ...

Now day’s functional verification is a very hot topic. With the growing complexity of modern digital systems and embedded system designs, the task of verification has become the key to achieving faster time-to-market requirement for such designs. Verification is the most important aspects of the ASIC design flow. It is estimated that between 40 to 70 percent of total development effort is consu...

We examine IBM’s exploitation of formal verification using RuleBase a formal verification tool developed by the IBM Haifa Research Laboratory. The goal of the paper is methodological. We identify an integrated methodology for the deployment of formal verification which involves three complementary modes: architectural verification, block-level verification, and design exploration.

We report on our experiences on the successful verification of a parameterized wireless fault-tolerant data aggregation protocol. We outline our verification method that involves automatic verification of a model of the node processing algorithm under system topology constraints. The presented work forms the basis for a generalization to verification rules for aggregation protocols that integra...