A transistor parameter extraction method is presented where the device heating during the measurement is taken into account. The method utilizes an electrothermal transistor model including thermal feedback, as well as a proper model for the heat diffusion from the active region of the transistor. Here a simple but physically justified model for the thermal spreading impedance of the transistor...

AbstructA direct approach to transistor sizing for minimizing the power consumption of a CMOS circuit under a delay constraint is presented. In contrast to the existing assumption that the power consumption of a static CMOS circuit is proportional to the active area of the circuit, it is shown that the power consumption is a convex function of the active area. Analytical formulation for the pow...

In present day skill, designing of low power systems has emerged as one of the vital theme of electronic industries due to the point that, power consumption is drawing much of the absorption in any very large scale integration (VLSI) chip design. Design of low power circuit for high performance is the necessary main concern of VLSI technique. This paper presents designing of Half Subtractor usi...

This paper describes the Differential Pass Transistor Pulsed Latch (DPTPL) which enhances D-Q delay and reduce power consumption using NMOS pass transistors and feedback PMOS transistors. The proposed flip-flop uses the characteristic of stronger drivability of NMOS transistor than that of transmission gate if the sum of total transistor width is the same. Positive feedback PMOS transistors enh...

Model Timo Veijola, Mikael Andersson*, and Antti Kallio Helsinki University of Technology, Faculty of Electrical Engineering, Circuit Theory Laboratory, Otakaari 5A, FIN-02150 Espoo, Finland. phone:+358-0-4512293, fax:+358-0-460224, e-mail:[email protected] *Nokia Research Center. P.O. Box 45, FIN-00211 Helsinki, Finland. Abstract| A simple method for transistor DC parameter extraction is prese...

With the increased need for low power applications, designers are being forced to employ circuit optimization methods that make tradeoffs between performance and power. In this paper, we propose a novel transistor-level optimization method. Instead of drawing the transistor channel as a perfect rectangle, this method involves reshaping the channel to create an optimized device that is superior ...

Transistor sizing is very important for determination of the circuit performance. As a result for providing fair evaluation, an optimal size of transistor is necessary. Genetic algorithm that is capable of reduction of search problem complexity uses the transistor sizing which is originally a kind of search problem in the large multidimensional search space for energy consumption optimization. ...