This paper introduces a novel technique for extracting the unique timing signatures of the FPGA configurable logic blocks in a digital form over the space of possible challenges. A new class of physical unclonable functions that enables inputs challenges such as timing, digital, and placement challenges can be built upon the delay signatures. We introduce a suite of new authentication protocols...

This paper presents a new cell matching method which could be effectively used for MUX-based FPGA technology mapping. In this method, a well organized cell library of a manageable size is constructed for each target architecture a priori, and cell matchings are performed by searching the corresponding entry in the library using integer comparison operations. Experimental results for some MCNC b...

A kind of hot spots detection alarm device and method is proposed in the paper about infrared thermal imaging, including the hardware design, algorithm, software realization. The hardware mainly includes the infrared thermal imaging camera and intelligent analysis board; the algorithm uses connected component detection method based on run length to extract target rectangle coordinates. This des...

For target recognition based on biologic vision, an application-specific stream SOC: MASA-MI is described in this paper. MASA-MI consists of several heterogeneous cores, and a stream accelerator core is used to accelerate matching image which consumes the most time in target recognition. We implemented it on Altera EP2S60 FPGA. Result shows the 166MHz MASA-MI provides a peak performance of 585 ...

In this paper we present a solution where only one FPGA is needed in a host coupled system, in which the FPGA can be reconfigured by a user application during run-time without loosing the host link connection. A hardware infrastructure on the FPGA and the software framework ACCFS (ACCelerator File System) on the host system is provided to the user which allow easy handling of reconfiguration an...

The design and field programmable gate array (FPGA)-based realisation of automatic censored cell averaging (ACCA) constant false alarm rate (CFAR) detector based on ordered data variability (ODV) is discussed here. The ACCA–ODV CFAR algorithm has been recently proposed in the literature for detecting radar target in non-homogeneous background environments. The ACCA–ODV detector estimates the un...

Scalability of Field Programmable Gate Array (FPGA) using spin MOSFET (spin FPGA) with magnetocurrent (MC) ratio in the range of 100% to 1000% is discussed for the first time. Area and speed of million-gate spin FPGA are numerically benchmarked with CMOS FPGA for 22nm, 32nm and 45nm technologies including 20% transistor size variation. We show that area is reduced and speed is increased in spin...

A significant obstacle to the widespread adoption of FPGAbased configurable computing hardware has been the difficulty of mapping applications onto this hardware. We are developing a software development system called CHAMPION to automate the process of mapping applications in the graphical software environment Khoros to multiple FPGA-based architectures. The work described here consists of the...

The DEFACTO project a Design Environment For Adaptive Computing TechnOlogy is a system that maps computations, expressed in high-level languages such as C, directly onto FPGA-based computing platforms. Major challenges are the inherent flexibility of FPGA hardware, capacity and timing constraints of the target FPGA devices, and accompanying speed-area trade-offs. To address these, DEFACTO combi...

The paper presents FPGA based design & implementation of Cholesky Decomposition for matrix calculation to solve least square problem. The Cholesky decomposition has no pivoting but the factorization is stable. It also has an advantage that instead of two matrices, only one matrix multiplied by itself. Hence it requires two times less operation. The Cholesky decomposition has been designed & sim...