The paper reports the implementation of a frequency synthesizer for system-on-chip (SOC) design. The epi-digital CMOS process is used to provide SOC solution. This work focuses on low-power consumption to achieve longer life-time of batteries. A 2.4GHz frequency synthesizer has been fabricated in 0.18μm epi-digital CMOS technology for ZigBee applications, which consumed 7.95mW from 1.8V supply....

System-on-Chip (SoC) design is an integration of multi million transistors in a single chip for alleviating time to market and reduce the cost of the design. It uses the concept of design reuse to increase the productivity with reduction in time. In this paper we present a platform for a low cost SoC design using Open Core SoC design methodology. It offers flexible way of using reusable cores w...

A study of the future trends in low-power System-on-Chip (SOC) designs is presented, based on the recently announced ITRS-2001 technology characteristics for both highperformance and low-power devices from 2001 to 2016. We forecast the logic/memory composition of a reference low-power PDA design with an area constraint of 1cm using both a bottom-up, power dissipation-constrained chip model and ...

The recent development of Field Programmable Gate Array (FPGA) System-on-Chip (SoC) architectures, with coarse-grain processors, embedded memories and Intellectual Property (IP) cores, offers high performance for computing power as well as opportunities for rapid system prototyping. These platforms require high-performance onand off-chip communication architectures for efficient and reliable in...

Embedded cores are being increasingly used in the designs of large system-on-a-chip (SoC). Because of the high complexity of SoC, the design verification is a challenge for system integrators. To reduce the verification complexity, the port-order fault (POF) model has been used for verifying core-based designs (Tung and Jou, 1998) . In this paper, we present an automatic-verification pattern ge...

With the increased emphasis on trimming production costs and time to market, first-pass silicon success has become a fundamental requirement for system-onchip (SoC) designs. First-pass silicon success can only be achieved through a comprehensive methodology for verifying the functional, timing, and analog/digital signal interface of a design. This article addresses the challenges associated wit...

With the increasing complexity of Multi-Core System-on-Chip (MCSoC) and its communications requirement, Network-on-Chip (NoC) has emerged as a solution of nonscalable shared bus schemes currently used in MCSoC implementation. Recently, a new NoC structure based on WKrecursive network was analyzed and compared to 2D Mesh structure based on several performance metrics such as packet losses, throu...

In heterogeneous tiled System-on-Chip architectures a Network-on-Chip is used to transport messages between processing elements. A reconfigurable network interface is used to connect the processing elements to the Network-on-Chip, converting the messages between both domains. This paper introduces the Hydra: a network interface for the MONTIUM TP, a coarse-grained reconfigurable processor desig...

Networks on Chip (NoC) has emerged as the paradigm for designing scalable communication architecture for Systems on Chips (SoCs). Avoiding the conditions that can lead to deadlocks in the network is critical for using NoCs in real designs. Methods that can lead to deadlock-free operation with minimum power and area overhead are important for designing application-specific NoCs. The deadlocks th...