this work is aimed to evaluate the role of nanoclay in the protective performance of an eco-friendly silane sol-gel layer applied on mild steel substrate in 0.1m sodium chloride solution. at the first step, the effect of ph of the silane solution, consisting of a mixture of γ-glycidoxypropiltrimethoxysilane and methyltriethoxysilane and tetraethoxysilane, on the coating performance was evaluate...

Progress in CMOS device technology has motivated the design of high-performance analog integrated circuits in standard CMOS processes. In particular, the high speed of submicron CMOS devices make them attractive for a variety of analog applications, including data converters, switched capacitor circuits, and low noise amplifiers [1,2,16]. However, recent reports have indicated that the measured...

background : the recognition of road traffic noise as one of the main sources of environmental pollution has led to develop models that enable to predict noise level from fundamental variables. traffic noise prediction models are required as aids for designing roads and highways. in addition, sometimes are used in the assessment of existing or envisaged changes in traffic noise conditions. in t...

This paper describes the noise reduction for fully integrated CMOS PLL. Since the Switching of large digital system introduces power supply or substrate noise which perturb the more sensitive blocks in a PLL. Which work as dominant jitter for VCO. This paper describes designs for both a PLL and a clock buffer that reduce sensitivity to supply noise for low-power applications. The supply noise r...

This paper presents a framework for modeling the phase noise in complementary metal–oxide–semiconductor (CMOS) ring oscillators. The analysis considers both linear and nonlinear operations, and it includes both device noise and digital switching noise coupled through the power supply and substrate. In this paper, we show that fast rail-to-rail switching is required in order to achieve low phase...

Techniques are presented to compactly represent substrate noise currents injected by digital networks. Using device-level simulation, every gate in a given library is modeled by means of the signal waveform it injects into the substrate, depending on its input transition scheme. For a given sequence of input vectors, the switching activity of every node in the Boolean network is computed. Assum...

This paper describes the PLL designed for the analog front-end of the silicon tuner in the cable modem system. The PLL is used to generate clocks (150-175MHz) for the DAC and hence the phase noise (jitter) requirement is very aggressive (15ps rms, which is less than 1 degree of integrated phase error). Low noise design for all the main blocks was a key to achieve this. Care was taken to reduce ...

background: noise is one of the most important harmful agents in work environment. noise pollution in oil refinery industries is related to workers' health. this study aimed to determine the overall noise pollution of an oil refinery operation and its frequency analysis to determine the control plan for a vent noise in these industries. methods: this experimental study performed in control unit...