The need for low power dissipation in portable computing and wireless communication is making design communities accept ultra low voltage CMOS processes. With the lowering of' supply voltage, the transistor thresholds (Vth) have to be scaled down to meet the performance requirements. However, such scaling can increase the leakage current through a transistor, thereby increasing the leakage powe...

The most fundamental operation of any processor is the addition. For any circuit there are two important parameters that comes into count is high speed and low power consumption. Hence the speed of various modules should be maximized to dominate overall performance. Depending upon these parameters various adders can be invented like Carry Look Ahead Adder(CLA),Carry Skip Adder(CSA) and Ripple C...

A circuit design methodology minimizing total power drain of a static complementary metal–oxide–semiconductor (CMOS) random logic network for a prescribed performance, operating temperature range, and short channel threshold voltage rolloff is investigated. Physical, continuous, smooth, and compact “Transregional” MOSFET drain current models that consider high-field effects in scaled devices an...

| The use of XOR gates has shown several advantages in modern circuit design, e.g. smaller representation size and better testability. In this paper we consider power consumption in XOR dominated circuits and compare such designs with traditional AND/OR logic. We investigate the suitability of using diierent delay models such as unit delay, fanout delay, and random delay in power estimation of ...

| The use of XOR gates has shown several advantages in modern circuit design, e.g. smaller representation size and better testability. In this paper we consider power consumption in XOR dominated circuits and compare such designs with traditional AND/OR logic. We investigate the suitability of using di erent delay models such as unit delay, fanout delay, and random delay in power estimation of ...

We present a chemical gas sensor based on a resonating cantilever beam in CMOS MEMS technology. The sensor is actuated employing electrothermal actuation. Thus, for a 300 μ m long beam vibration amplitudes of 6.5 nm per mW heating power are achieved. The vibrations are detected with piezoresistors in a Wheatstone bridge scheme. Detection sensitivities above 200 μ V per mW heating power are meas...

The scaling down of technology in CMOS circuits, results in the down scaling of threshold voltage thereby increasing the sub-threshold leakage current. LECTOR is a technique for designing CMOS circuits in order to reduce the leakage current without affecting the dynamic power dissipation, which made LECTOR a better technique in leakage power reduction when compared to all other existing leakage...

Dynamic logic style is used in high performance circuit designs because of its faster speed and lesser transistor requirement as compared to static CMOS logic style. Dynamic logic has inherent disadvantages like less noise immunity and high power consumption. In this paper we have proposed a novel circuit technique for implementing dynamic gate. The proposed circuit has very less power dissipat...

In contemporary and future embedded as well as high-performance microprocessors, power consumption is one of the most important design considerations. Because in current technologies the dynamic power consumption dominates the static power consumption, voltage scaling is an effective technique to reduce the power consumption. The most common way to reduce the power consumption of multi-processo...