Due to the substantial impact embedded Static Random Access Memory (SRAM)s have on overall system and their relatively limited design, it is essential manage SRAM trade-offs strategically. SRAMs power, performance density in general. In all applications, three dimensions are necessary some extent; accordingly, design must incorporate most crucial system-specific requirements when developing SRA...

In this study, a three-dimensional ''atomistic " coupled device-circuit simulation is performed to explore the impact of process-variation-effect (PVE) and random-dopant-fluctuation (RDF) on static noise margin (SNM) of 16-nm complementary metal–oxide–semiconductor (CMOS) static random access memory (SRAM) cells. Fluctuation suppression approaches, based on circuit and device viewpoints, are fu...

In-memory computing (IMC) aims to solve the performance gap between CPU and memories introduced by memory wall. However, it does not address energy wall problem caused data transfer over hierarchies. This paper proposes data-locality management unit (DMU) efficiently from a DRAM computational SRAM (C-SRAM) allowing IMC operations. The DMU is tightly coupled within C-SRAM allows one align struct...

This paper proposes a 7T SRAM that realizes a blocklevel instantaneous comparison feature. The proposed SRAM is useful for operation results comparison in dual modular redundancy (DMR). The data size that can be instantaneously compared is scalable using the proposed structure. The 1-Mb SRAM comprises 16-Kb blocks in which 8-Kb data can be compared in 130.0 ns. The proposed scheme reduces energ...

To store anything in the form of bits, we need memory. Memory can be formed with the integration of large number of basic storing element called cell. SRAM cell is one of the basic storingelement. There is further scope of improving the performance of SRAM cell.This paper provides a review of various proposed schemes used to improve the stability of SRAM cell and to reduce its area and power co...

Ternary Content Addressable memory is a type of memory that allows the memory to be searched by content rather than by address. It performs high speed lookup operations within a single clock cycle. But when compared to RAM technology the conventional TCAM circuitry has certain limitations such as low access time, low storage capacity, circuit complexity and high cost. So we can use the benefits...

Purpose: CMOS devices are scaling down to nano ranges resulting in increased process variations and short channel effects which not only affect the reliability of the device but also performance expectations. The SRAM design uses the smallest transistors possible and is also susceptible to reliability issues and process variations, making it an ideal benchmark circuit to compare the two technol...

Computing-in-memory (CIM) is a promising approach to reduce latency and improve the energy efficiency of multiply-and-accumulate (MAC) operation under memory wall constraint for artificial intelligence (AI) edge processors. This paper proposes an focusing on scalable CIM designs using new ten-transistor (10T) static random access (SRAM) bit-cell. Using proposed 10T SRAM bit-cell, we present two...

One of the major reliability concerns in nano-scale VLSI design is the time dependent Negative Bias Temperature Instability (NBTI) degradation. Due to the higher operating temperature and increasing vertical oxide field, threshold voltage (Vt) of PMOS transistors can increase with time under NBTI. In this paper, we examine the impact of NBTI degradation in memory elements of digital circuits, f...

Semiconductor manufacturing process scaling increases leakage and transistor variations, both of which are problematic for static random access memory (SRAM). Since SRAM is a critical component in modern CMOS integrated circuits, novel approaches to addressing these problems are needed. Here, six and seven transistor SRAM cells are presented that do not suffer from reduced stability when read. ...