Abstract In this work, we investigate and analyze the impact of gate tunneling on dynamic behaviors of partially depleted SOI CMOS with the aid of the physically accurate BSIMPD model. We examine in particular the impact of gate tunneling on the history dependence of inverter delays. The examination reveals key requirements for capturing the history effect in SPICE modeling. This study suggests...

This paper introduces a new approach to pattern dependent static power estimation in logic blocks, which are realized ‘on-the-fly’ in a library-free design environment. A static current model is first developed at the transistor level and then extended to the logic gate level and finally the logic block level. For varying transistors widths and input stimuli, the transistor level model has perf...

Evidence indicates that sleep plays an important role in learning and memory, and disruption of sleep especially seems to interfere with hippocampal memory processes. Social transmission of food preference (STFP), a natural test of paired associative learning, has been shown to be dependent on the hippocampus. While social transmission of food preference is not a novel task, it has not been use...

Version 5, December 2004 The promise that comes from supporting compact modeling in Verilog-A/MS is the release of the designers from the tyranny of proprietary models. However, that promise is only half satisfied if we only support the model equations in Verilog-A/MS. While having a industry standard language for expressing model equations is critically important, it does not address the probl...

A new SPICE-compatible behavioral model for an arbitrary nonlinear magnetic circuit was developed and verified experimentally. The proposed model was used to analyze a current controlled magnetic inductor behavior. The nonlinearity of the ferromagnetic medium was reproduced by applying the core manufacturer data. Close agreement was obtained between the simulation and experimental results.

This chapter presents an introduction to the area of accelerated transistorlevel (‘fast-SPICE’) simulation for automated verification and characterization of integrated circuits (ICs) from technologist’s perspective. It starts with outlining goals, expectations and typical usage models for fast-SPICE simulators, stressing how they differ from regular SPICE tools. It continues with presenting an...