A group testing-based BIST technique to identify faulty hard cores in FPGA devices is presented. The method provides for isolation of faults in embedded cores as demonstrated by experiments on the Virtex-5 family of Xilinx FPGAs. High-level HDL code is developed to instantiate a Finite State Machine (FSM) which generates the test inputs for the Blocks Under Test (BUTs). The BUTs are divided int...

This paper presents a novel hardware architecture for principal component analysis. The architecture is based on the Generalized Hebbian Algorithm (GHA) because of its simplicity and effectiveness. The architecture is separated into three portions: the weight vector updating unit, the principal computation unit and the memory unit. In the weight vector updating unit, the computation of differen...

Reconfigurable architecture provides a high performance computing paradigm. We can implement the compute-intensive functions into reconfigurable devices to optimize the application performance. In current reconfigurable hardware designs, the function-level reconfigurable hardware has high reusability and low maintenance cost. However, the sharing mechanism and the function invocation interface ...

A low-cost machine vision system with hardware capabilities of image processing is developed in this research. Several image process algorithms are designed for the developed vision system, namely, image quality selection, image recovery and resize, and image segmentation. All of these mathematical algorithms are programmed and implemented in a microchip using SOPC design tools. Furthermore, th...

An architecture for real time face recognition using weighted modular principle component analysis (WMPCA) is presented in this paper. The WMPCA methodology splits the test face horizontally into sub-regions and analyzes each sub-region separately using PCA. The final decision is taken based on a weighted sum of the errors obtained from each region. This is based on assumption that different re...

The paper proposes a comparison between hardware and software solutions for resource partitioning in the scenario of a multi-core based mixed criticality application. A reference avionic application has been implemented in two versions: one using a software partitioning solution and one using a hardware partitioning solution. Both versions of the system have been evaluated using fault injection...

This paper presents a novel phase unwrapping architecture for accelerating the computational speed of digital holographic microscopy (DHM). A fast Fourier transform (FFT) based phase unwrapping algorithm providing a minimum squared error solution is adopted for hardware implementation because of its simplicity and robustness to noise. The proposed architecture is realized in a pipeline fashion ...