This paper presents an adaptive digital resolution improvement method for extrapolating and recursive analog-to-digital converters (ADCs). The presented adaptively enhanced ADC (AE-ADC) digitally estimates the digital equivalent of the input signal by utilizing an adaptive digital filter (ADF). The least mean squares (LMS) algorithm also determines the coefficients of the ADF block. In this sch...

This paper presents a 10-bit 160-MSPS 2.5-V digital to analog converter (DAC) and is implemented in TSMC 0.25μm CMOS technology. A segmented current steering architecture is used with optimized performance for speed, resolution, power consumption and area. The DAC can be operated up to 160MHz sampling frequency and the settling time is less than 4.8 ns. The differential nonlinearity (DNL) and i...

A 4 order subsampled RF LC Σ∆ ADC suitable for Software Defined Radio applications is presented. The ADC is clocked at 3.2GHz and centered at 2.4GHz. The simplicity of the ADC architecture combined with the subsampling technique result in a significant performance enhancement and power consumption reduction. A sine-shaped feedback DAC is used, not only for its reduced sensitivity to clock jitte...

This paper presents a 14bit 500MS/s SHA-less pipelined analog-to-digital converter (ADC) implemented in 40nm CMOS. A high-linearity pseudo-differential push-pull input buffer with an anti-oscillation technique and nonlinear parasitism eliminate is proposed to stably drive the stages while keeping low distortion. Moreover, digital controlled aperture-error calibration also employed offset of com...

There is a need for a universal dynamic model of analog-to-digital converters (ADC’s) aimed for postcorrection. However, it is complicated to fully describe the properties of an ADC by a single model. An alternative is to split up the ADC model in different components, where each component has unique properties. In this paper, a model based on three components is used, and a performance analysi...

A modification of the background digital calibration procedure for A/D converters by Li and Moon is proposed, based on a method to improve the speed of convergence and the accuracy of the calibration. The procedure exploits a colored random sequence in the calibration algorithm, and can be applied both for narrowband input signals and for baseband signals, with a slight penalty on the analog ba...

A spectral built-in self test (BIST) solution for integrated cellular RF transmitters is presented that enables on-chip verification of PLL spectral performance. Multi-tone FM test signals with a spurious-free dynamic range (SFDR) of 60 dB are generated without compromising the performance of the RF transmitter itself. The RF signal is demodulated and digitized in an on-chip digital FM discrimi...

A 10b 150MS/s 0.4mm pipeline ADC is implemented in a 45nm CMOS process. The input SHA, employing four charge-redistributed capacitors, converts single-ended or differential input signals of 1.2Vpp to differential outputs of 0.8Vpp for a low supply voltage of 1.1V. The process-insensitive high-gain amplifiers in the SHA and MDACs are based on gainboosting, pseudo-differential output pair, and co...

A 1.6 GS/s Track and Hold circuit that produces 16 interleaving, 100 MS/s voltage buffered output signals is presented. The achieved SFDR for a 950 MHz full scale input signal is 50 dB. Phase alignment is 0.4 ps RMS and aperture uncertainty is 1 ps RMS. The chip includes two Analog to Digital Converters and a Switching Matrix to accommodate measurement of all sampled output signals and their ti...

Measurement and calibration of an analog-to-digital converter (ADC) using a histogram-based method requires a large volume of data and a long test duration, especially for a high resolution ADC. A fast and accurate calibration method for pipelined ADCs is proposed in this research. The proposed calibration method composes histograms through the outputs of each stage and calculates error sources...