The Internet of Things (IoT) has become more prevalent in recent years and is an integral part everyday life. Thus, the need for ultralow-power sensors processing units dramatically increased. continuous scaling CMOS transistors resulted severe subthreshold leakage high power density issues. In years, microelectromechanical (MEM) relays have attracted research interests. They are viewed as prom...

Random pattern testing methods are known to result in poor fault coverage for most sequential circuits unless costly circuit modiication methods are employed. In this paper we propose a novel approach to improve the random pattern testability of sequential circuits. We introduce the concept of holding signals at primary inputs and scan ip-ops for a certain length of time instead of applying a n...

AbstructA standard cell library typically contains several versions of any given gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed on the circuit. After presenting an efficient algorithm for combinational circuits, we exa...

This research is motivated by the Circuit Value Problem; this problem is well known to be inherently sequential. We consider Boolean circuits with descriptions length d that consist of gates with a xed fan-in f and a constant number of inputs. Assuming uniform distribution of descriptions, we show that such a circuit has expected depth O(log d). This improves on the best known result. More prec...

A standard cell library typically contains several versions of any given gate type, each of which has a di erent gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed on the circuit. After presenting an e cient algorithm for combinational circuits, we examine the pr...

We present a methodology for the watermarking of synchronous sequential circuits that makes it possible to identify the authorship of designs by imposing a digital watermark on the state transition graph (STG) of the circuit. The methodology is applicable to sequential designs that are made available as firm intellectual property, the designation commonly used to characterize designs specified ...

This paper proposes a detailed design analysis of sequential circuits for quantum-dot cellular automata (QCA). This analysis encompasses flip-flop (FF) devices as well as circuits. Initially, a novel RS-type FF amenable to a QCA implementation is proposed. This FF extends a previous threshold-based configuration to QCA by taking into account the timing issues associated with the adiabatic switc...

Recently developed methods for power estimation have primarily focused on combinational logic. In this paper, we present a framework for the eecient and accurate estimation of average power dissipation in sequential circuits. Switching activity is the primary cause of power dissipation in CMOS circuits. Accurate switching activity estimation for sequential circuits is considerably more diicult ...

In this work we study classes of optimization problems that require inherently sequential algorithms to solve exactly but permit highly parallel algorithms for approximation solutions. NC is the class of computational problems decidable by a logarithmic space uniform family of Boolean circuits of bounded fan-in, polynomial size, and polylogarithmic depth. Such problems are considered both “effi...