This paper presents a 10-bit pipeline ADC using double sampling technique to achieve a conversion rate of 40 MS/s at 2.5-V supply. The opamps are two-stage with folded-cascode as the first stage and feature techniques such as common-mode stabilized active load, crosscoupled cascode connection, and close-loop pole placement. MOS switches are driven by bootstrapping circuits that do not subject t...

This paper proposes a methodology for the parametric design of operational transconductance amplifiers. In the proposed methodology, amplifier sizing is performed in two stages: an equation-based design scheme performs an approximate design, followed by optimization of the design results with genetic algorithms. The feasibility of this method was investigated with extensive simulation. For demo...

Floating Gate MOS (FGMOS) transistors can be very well implemented in lieu of conventional MOSFET for design of a low-voltage, low-power current mirror. Incredible features of flexibility, controllability and tunability of FGMOS yields better results with respect to power, supply voltage and output swing. This paper presents a new current mirror designed with FGMOS which exhibit high output imp...

The cascode NMOS architecture has been tested by the Human Body Model (HBM), Machine Model (MM) and Transmission Line Pulse Generator (TLP) in this paper. For the TLP, detailed silicon data have been analyzed well in many parameters, such as the first triggeringon voltage (Vt1), the first triggering-on current (It1), the holding voltage (Vh), and the TLP I-V curve. Besides the above three kinds...

This paper presents a 30dBm (1W) class-E power amplifier projected in a standard 0.18-μm CMOS technology. The power amplifier (PA) consists in two differentials stages. The main stage employs a cascode class-E RF power amplifier with a self-biasing circuit. The driver stage uses the technique of Injection-Locking to substantially reduce the input power signal, maintaining a high gain. At 2.45 G...

This paper examines architectural techniques for providing concurrent error detection in self-timed VLSI pipelines. Signal pairs from Differential Cascode Voltage Switch Logic are compared with a checker that is composed of a tree of dual-rail (morphic) comparators to detect errors and signal completion. An efficient implementation is shown that compares favorably in speed and area with convent...