The thesis extensively revolves around embedded FPGAs (eFPGAs). It conducts detailed survey focused on programmable technologies to investigate potentials and challenges of eFPGAs and probable failure reasons of several past attempts of different kinds. Based on the survey knowledge, technology independent soft eFPGAs of FPGA-like mesh-based classical architecture with standard RTL programming ...

Software generated from finite state machines targeted for standard embedded systems processors generally displays poor execution speeds. This paper evaluates an architecture that couples a standard processor with a reconfigurable unit in order to improve the execution speed of the generated code. A method for automatically partitioning the code is presented along with results obtained from sim...

Wire delay is rapidly becoming a major bottleneck in reconfigurable systems, creating a significant gap between the clock rates of reconfigurable logic and custom circuits. In this paper, we describe the design of the reconfigurable clusters on the Amalgam clustered programmable-reconfigurable processor. Amalgam’s reconfigurable clusters are divided into four segments of reconfigurable logic, l...

Self-reconfigurable robots are designed so that they can change their external shape without human intervention. One general way to achieve such functionality is to build a robot composed of multiple, identical unit modules. If the modules are designed so that they can be assembled into rigid structures, and so that individual units within such structures can be relocated within and about the s...

This paper describes an experiment which aims to reveal the potential impact on performance yielded by augmenting a TriMedia-CPU64 processor with a multiple-context FPGA core. We first propose an extension of the TriMediaCPU64 architecture, which consists of a Reconfigurable Functional Unit and its associated instructions. Then, we address the decoding of variable-length codes on such extended ...

Wavelet-based image compression has been suggested previously as a means to evaluate and compare both traditional and reconfigurable computers in terms of performance and resource requirements. We present a reconfigurable implementation of such an application that not only achieves a performance comparable to that of recent CPUs, but does so at a fraction of their power consumption.

The extensive use of reconfigurable computing devices has imposed a new category of processors, the dynamic instruction set processors (DISPs) that customize their instruction sets dynamically to the application needs. One of the major drawbacks of DISPs is the reconfiguration time needed to alter the instruction set, which is directly added to the program execution time discouraging the use of...

The paper suggests architecture of a reconfigurable processor, which can be customized for implementing different search algorithms over discrete matrices. Such algorithms might be used for solving various problems of combinatorial optimization, such as covering, Boolean satisfiability, etc. The proposed architecture contains memory blocks for binary or ternary matrix, general-purpose registers...

A prototype machine of the Star parallel processing system is being built. The Star system employs reconfigurable interconnection networks and a distributed control mechanism for supercomputing. Progress on the design of interconnection networks, interface unit, operating system kernel and instruction set, and resource allocation is reported here to delineate concepts and status.