Our system is designed to cope with water depths of around 100m, meaning the number of measurements taken during one dive can be significant. Storage is thus required for the large volumes of measurement data: not only those collected by the diving unit but also from light and acceleration sensors placed on the top of the buoy. System data also needs to be saved; for example, the energy produce...

USIMM, the Utah SImulated Memory Module, is a DRAM main memory system simulator that is being released for use in the Memory Scheduling Championship (MSC), organized in conjunction with ISCA-39. MSC is part of the JILP Workshops on Computer Architecture Competitions (JWAC). This report describes the simulation infrastructure and how it will be used within the competition.

This report presents our exploratory efforts for managing main memory power-aware chips. Current stateof-the-art power-aware DRAM chips offer various power modes (active, standby, nap, and powerdown) in order to provide a potential to limit power consumption in the face of increasing demand for performance. Our goal in this study is to utilize and exploit these various power modes for the most ...

Sensor-based navigation is one of the most important researches for mobile robots domain and then there are many research works for sensor-based navigation. We propose the insects inspired landmark navigation to pinpoint the target position in this paper. There exit several research works such as snapshot model and average landmark model which request the absolute bearing information (compass) ...

Emerging portable devices relay on DRAM/flash memory system to satisfy requirements on fast and large data storage and low-energy consumption. This paper presents a novel approach to reduce energy of memory system, which unlike others, lowers energy of refresh operation in DRAM. The approach is based on two key ideas: (1) DRAM-based flash cache that keeps dirty pages to reduce the number of acc...

Interactive visualization of very large volume data has been recognized as a task requiring great effort in a variety of science and engineering fields. In particular, such data usually places considerable demands on run-time memory space. In this paper, we present an effective 3D compression scheme for interactive visualization of very large volume data, that exploits the power of wavelet theo...

This paper explores the energy and delay issues that occur when some or all of the local storage is moved out of the embedded device, and into a remote network server. We demonstrate using the network to access remote storage in lieu of local DRAM results in significant power savings. Mobile applications continually demand additional memory, with traditional designs increasing DRAM to address t...

This research addresses a major gap in our conceptual understanding of synaptic and brain-like network dynamics. Over the course of several years we have designed and implemented increasingly complex and powerful brain-like simulators which apply recent advances in computer and networking technology towards the goal of understanding brain function in terms of pulse-coded information networks. T...

Dual-layer resistive switching devices with horizontal W electrodes, vertical Pd electrodes and WOx switching layer formed at the sidewall of the horizontal electrodes have been fabricated and characterized. The devices exhibit well-characterized analog switching characteristics and small mismatch in electrical characteristics for devices formed at the two layers. The three-dimensional (3D) ver...

This paper describes an early memory yield prediction model using a memory sensitive area model. The proposed sensitive area prediction model calculates the sensitive area of a memory block for a given process technology and memory capacity. The model is capable of predicting the yield of a memory block in the early design phase without the detailed knowledge of the physical layout. The use of ...