In this article, a new radix-2 signed-digit number (Radix-2 sub signed-digit number) is defined and its properties for hardware realization are discussed. Until now, high speed calculation method with Radix-2 signed-digit numbers is proposed, but this method used “Compares With 2” to calculate carry. “Compares with 2” is a very simple method, but it needs very complicated hardware especially wh...

In this article, magnitude relation properties of Radix-2k SD number are discussed. Until now, the Radix-2k SD Number is proposed for the high-speed calculations for RSA Cryptograms. In RSA Cryptograms, many modulo calculations are used, and modulo calculations need a comparison between two numbers. In this article, we discussed about a magnitude relation of Radix-2k SD Number. In the first sec...

This note presents two new fast discrete cosine transform computation algorithms: a radix-3 and a radix-6 algorithm. These two Manuscript received November 21, 1991; revised January 4, 1993. The authors are with the Department of Electronic Engineering, Hong IEEE Log Number 921 1527. Kong Polytechnic, Hung Hom, Kowloon, Hong Kong. new algorithms are superior to the conventional radix-2 algorith...

Viterbi decoders employed in digital wireless communications are complex and dissipate large amount of power. In this paper, we investigate power dissipation of Radix-4 Viterbi decoder and SST (Scarce State Transition) Radix-4 Viterbi decoder with changing the constraint length K (namely, K=3, 4). We presents a low power, high-rate Viterbi decoder using SST scheme and Radix-4 trellis. The SST m...

We show the importance of sequential sorting in the context of in memory parallel sorting of large data sets of 64 bit keys. First, we analyze several sequential strategies like Straight Insertion, Quick sort, Radix sort and CC-Radix sort. As a consequence of the analysis, we propose a new algorithm that we call Sequential Counting Split Radix sort, SCS-Radix sort. SCS-Radix sort is a combinati...

We present a radix-4 static CMOS full adder circuit that reduces the propagation delay, PDP, and EDP in carry-based adders compared with using a standard radix-2 full adder solution. The improvements are obtained by employing carry look-ahead technique at the transistor level. Spice simulations using 45 nm CMOS technology parameters with a power supply voltage of 1.1 V indicate that the radix-4...

In this paper, we present a 128-point FFT/IFFT processor for ultrawideband (UWB) systems. The proposed FFT is developed based on the higher radix -2 4 . It reduces computational complexity and hardware requirement compared to conventional radix -2 FFT. Since the proposed pipelined architecture for 128-point FFT is designed using mixed-radix (16+8) multipath delay feedback (MRMDF). The proposed ...

SRT dividers are common in modern floating point units. Higher division performance is achieved by retiring more quotient bits in each cycle. Previous research has shown that realistic stages are limited to radix-2 and radix-4. Higher radix dividers are therefore formed by a combination of low-radix stages. In this paper, we present an analysis of the effects of radix-2 and radix-4 SRT divider ...

This investigation proposes the novel radix4 and radix-4 algorithms with the low computational complexities of the radix-16 and radix-64 algorithms but the lower hardware requirement of the radix-4 algorithm. Base on the serial delay feedback path pipeline architecture, the proposed design adopts a multiplierless radix-4 butterfly structure to support 4096-point FFT/IFFT computations. Moreover,...