The speed of SRT-type dividers is mainly determined by the complexity of the quotient-digit selection , so that implementations are limited to low-radix stages. We present a scheme in which the quotient-digit is speculated and, when this speculation is incorrect , a rollback or a partial advance is performed. This results in a division operation with a shorter cycle time and a variable number o...

The speed of high-radix digit-recurrence dividers is mainly determined by the hardware complexity of the quotient-digit selection function. In this paper we present a scheme that combines the area efficiency of bundled data with data-dependent computation time. In this scheme the selection function is very simple and may be implemented using a fast adder. This function speculates the result dig...

In this paper, we propose the grouped scheme, which can be specially applied to compute the pruning fast Fourier transform (pruning FFT) with power-of-two partial transformation length. The group-based pruning FFT algorithm applies the scheme of the grouped frequency indices to accelerate computations of selected discrete Fourier transform (DFT) outputs. The proposed pruning FFT algorithm has f...

This investigation proposes the novel radix4 and radix-4 algorithms with the low computational complexities of the radix-16 and radix-64 algorithms but the lower hardware requirement of the radix-4 algorithm. Base on the serial delay feedback path pipeline architecture, the proposed design adopts a multiplierless radix-4 butterfly structure to support 4096-point FFT/IFFT computations. Moreover,...

Modern RISC processors provide a special instruction { the fused multiplyadd (FMA) instruction a b c { to perform both a multiplication and an addition operation at the same time. In this paper newly developed radix-2, radix-4, and split-radix FFT algorithms that optimally take advantage of this powerful instruction are presented. All oating-point operations of these algorithms are executed as ...

In this work we derive two families of radix-4 factorizations for the FFT (Fast Fourier Transform) that have the property that both inputs and outputs are addressed in natural order. These factorizations are obtained from another two families of radix-2 algorithms that have the same property. The radix-4 algorithms obtained have the same mathematical complexity (number of multiplications and ad...

Background. A scheme for format-preserving encryption (FPE) is supposed to do that which a conventional (possibly tweakable) blockcipher does—encipher messages within some message space X—except that message space, instead of being something like X = {0, 1}128, is more general [1, 3]. For example, the message space might be the set X = {0, 1, . . . , 9}16, in which case each 16-digit plaintext ...

The 4.3BSD Reno release introduced the reduced radix tree for routing table to support variable length addresses and best-match based lookups instead of the hash-based scheme of the 4.3BSD Tahoe release. The lookup and maintenance algorithm of Radix is, however, complicated due to support of non-continuous subnet-mask and it is not easy to understand the source code. In order to support classle...

This paper presents a novel split-radix fast Fourier transform (SRFFT) pipeline architecture design. A mapping methodology has been developed to obtain regular and modular pipeline for split-radix algorithm. The pipeline is repartitioned to balance the latency between complex multiplication and butterfly operation by using carry-save addition. The number of complex multiplier is minimized via a...

A 2-bit Booth encoder with Josephson Transmission Lines (JTLs) and Passive Transmission Lines (PTLs) is designed. The Booth encoding method is one of the algorithms to obtain partial products. With this method, the number of partial products decreases down to the half compared to the AND array method. The circuit area of the multiplier designed with the Booth encoder method is compared to that ...