This new method of built-in self-test (BIST) for sequential cores on a system-on-a-chip (SOC) generates test patterns using a real-time program that runs on an embedded processor. Alternatively, the same program can be run on an external low-cost tester. This program generates patterns using circuit-specific spectral information in the form of one or more Hadamard coefficients. The coefficients...

Multithreaded architectures hold the promise of high performance through an overlap of computation and communication. This paper explores how the overlap in multithreaded execution aaects the performance of processor, memory, and network subsystems; what are the critical parameters to ensure high processor performance; and what is the performance impact of optimizations of the workload and arch...

Recent advances in processor technology allow multiple processors to reside within the same chip, allowing high performance per watt. Currently the Cell Broadband Engine has the leading performance-per-watt specifications in its class. Each Cell processor consists of a PowerPC Processing Element (PPE) working together with eight Synergistic Processing Elements (SPE). The SPEs have 256KB of memo...

Code size is a primary concern in the embedded computing community. Minimizing physical memory requirements reduces total system cost and improves performance and power efficiency. VLIW processors rely on the compiler to statically encode the ILP in the program before its execution, and because of this, code size is larger relative to other processors. In this paper we describe the co-design of...

This paper presents the New Systolic Language as a general solution to the problem systolic programming. The language provides a simple programming interface for systolic algorithms suitable for di erent hardware platforms and software simulators. The New Systolic Language hides the details and potential hazards of inter-processor communication, allowing data ow only via abstract systolic data ...

This paper investigates issues which impinge on the design of static instruction schedulers for micronetbased asynchronous processor (MAP) architectures. The micronet model exposes both temporal and spatial concurrency within a processor. A list scheduling algorithm is described which has been optimtsed with MAP-specific heuristics. Their performance on some program graphs are presented and con...

We study the hardware cost of implementing hash-tree based verification of untrusted external memory by a high performance processor. This verification could enable applications such as certified program execution. A number of schemes are presented with different levels of integration between the on-processor L2 cache and the hash-tree machinery. Simulations show that for the best of our method...

We study the hardware cost of implementing hash-tree based verification of untrusted external memory by a high performance processor. This verification could enable applications such as certified program execution. A number of schemes are presented with different levels of integration between the on-processor L2 cache and the hash-tree machinery. Simulations show that for the best of our method...

This paper represents the combination of Reduced Instruction Set Computer (RISC) system using VHDL and implement. This paper presents a RISC processor designing to achieve various arithmetic operations. The RISC is a 20 bit processor. KeywordsArithmetic Logic(AL), Central Processing Unit(CPU), Control Unit(CU), Field Programmable Logic Array(FPGA), General Purpose Register(GPR), Program Counter...