A circuit design for a new high speed and Low Power 4-bit Braun Multiplier is presented. The multiplier is implemented by using different power reduction techniques. To design a multiplier it is necessary to design an AND gate and Full Adder circuit using the power reduction techniques is presented. The design uses CMOS digital circuits in order to reduce the power dissipation while maintaining...

Power consumption and delay are two important considerations for VLSI systems. The objective of this project is to reduce the power and to reduce the delay which increases the speed. Adders are very important components in many applications such as microprocessor and digital signal processing (DSP) architectures. Full Adder is one of the core elements. It used in many of the complex arithmetic ...

This paper examine the effect of subthreshold voltage in function, delay, power and energy. Benchmark circuit c6288 in 45 nm technology is used in this design. The focus of this work is to find the optimal power delay product of benchmark circuit at subthreshold operation. The simulation was done using HSPICE. Results show that the 45nm cell libraries support the subthreshold operation of elect...

Unlike the existing views that was introduced the existence of delay caused by the transmission of wide area measurement system data (WAMS) into the controllers input of the power oscilation damping (POD) by communication networks as a reason for poor performance of the POD controllers. This paper shows that the presence of time delay in the feedback loop may improve the performance of a POD co...

In this paper, a high performance pulse Triggered flipflop design is presented. The proposed design reduces the number of transistors stacked in the discharging path and also reduces the overall switching delay. This enhanced pulse triggered low-power flip flop (EPTLFF) avoids unnecessary internal node transitions to improve the power consumption as compared to previously designed circuits. A 4...

VLSI technology has developed over the years thereby enhancing the performance of chips in terms of three basic constraints viz. delay, power and area. Gate Diffusion Input technique is one such method which attempts to minimize the delay and power consumed by the circuit. The paper basically focuses on the implementation of the technique on combinational logic circuits and experimental delay r...

In this paper, the various low power full adder circuits with high speed operation have been analyzed. The adder is the basic building blocks of arithmetic circuits, so a small amount of power or delay reduction leads to greatest power saving or better performance of the circuit. Various design techniques are available for low power high speed full adders. All the adders are simulated using tan...

Two high performance level restoration circuits are proposed, which outperform the existing level restoration circuits with cross-coupled PMOS, in terms of power dissipation and delay. The first configuration employs a back-bias scheme in order to eliminate the stand-by leakage caused by the low-swing input. The second one adopts a bootstrapping technique, in order to restore the low swing sign...

Recently reported logic style comparisons based on full-adder circuits claimed complementary pass-transistor logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different logic cells, as well as the use of realistic circuit arrangements demonstrate CMOS to be superior to CPL in m...

Recovered Energy Logic (REL) is a new family of logic that charges and discharges capacitive logic nodes in an ideally lossless fashion. To accomplish this, REL uses an AC waveform as both the system power supply and a two-phase clock. Unlike mainstream logic circuits, REL circuits require substantial current from all three terminals of a transistor. This makes BJTs and MESFETs a natural choice...