Network-on-Chip (NoC) is the interconnection platform that answers the requirements of the modern on-Chip design. Small optimizations in NoC router architecture can show a significant improvement in the overall performance of NoC based systems. Power consumption, area overhead and the entire NoC performance is influenced by the router buffers. Resource sharing for on-chip network is critical to...

Current trend of technology scaling makes it possible to put a huge number of transistors on a single die. While dynamic power consumption can benefit from technology scaling, static power consumption get worse, thus making the latter the dominant factor of power consumption in future microprocessor systems. As on-chip cache memories require the most part of chip area and number of transistors,...

Current trend of technology scaling makes it possible to put a huge number of transistors on a single die. While dynamic power consumption can benefit from technology scaling, static power consumption get worse, thus making the latter the dominant factor of power consumption in future microprocessors system. As on-chip cache memories require the most part of chip area and number of transistors,...

This paper proposes a low-power and area-efficient shift register using pulsed latches. The area and power consumption are reduced by replacing flip-flops with pulsed latches. This method solves the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed clock signal. The shift register uses a small num...

Energy consumption in Wireless Sensor Network (WSN) is one very critical factor in its operation because of being battery powered and the need to operate continuously over a long period of time. WSN nodes are generally miniaturized that make them light and mobile and non intrusive, but this leads to have a smaller space to carry bulky power sources. 6LoWPAN protocol, a version of WSN that can r...

A domino logic technique is designed to meet the critical concern of the VLSI era with convenience and high microelectronic devices, power consumption of the digital circuit. The design and circuit performance improves the power consumption, area and delay of the circuit. If there is a path delay in wide fan multiplexers, then path reads out becomes more difficult and there is high power consum...

In this work a new resistorless sub-bandgap voltage reference topology is presented. It is a self-biased and small area circuit that works in the nano-ampere consumption range, and under 1 V of power supply. The behavior of the circuit is analitically described, a design methodology is proposed and simulation results are presented for a standard 0.18 μm CMOS process. A reference voltage of 463 ...

Pseudorandom number generators (PRNGs) are very important for EPC Class 1 Gener­ ation 2 (EPC C1 G2) Radio Frequency Identification (RFID) systems. A PRNG is able to provide a 16-bit random number that is used in many commands of the EPC C1 G2 standard, and it can also be used in future security extensions of the EPC C1 G2 standard, such as mutual authentication protocols between the readers an...

Requirement on number of register file (RF) ports in parallel processors poses a stringent challenge on RF design. Access time, power consumption and silicon area of the RF are strongly related to the micro-architecture and the number of access ports. A clustered register file with global registers is presented in this paper. Circuit techniques and scheduling sequences are also presented to enh...