Software pipelining is becoming widely used as a loop execution model for microprocessors supporting a high instruction level parallelism. In this paper we describe a heuristic method for software pipelining, named Graph Traverse Software Pipelining (GTSP), that divides the scheduling problem in two phases: scheduling on a graph and code generation. The first phase encapsulates the NP-complete ...

In this paper, we propose an integrated approach for register-sensitive software pipelining. In this approach, the heuristics proposed in the stage scheduling method of Eichenberger and Davidson [4] are integrated with the iterative scheduling method to obtain schedules with high initiation rate and low register requirements. The performance of our integrated software pipelining method was anal...

Software tools for working with argument generally exist as large systems that wrap their entire feature set in the application as a whole. This approach, while perfectly valid, can result in users having to use small parts of multiple systems to carry out a specific task. In this paper, we present a series of web services, that each encapsulate small pieces of functionality for working with ar...

© Copyright Hewlett-Packard Company 1992 Compilers for VLIW and superscalar processors have to expose instruction-level parallelism to effectively utilize the hardware. Software pipelining is a scheduling technique to overlap successive iterations of loops, while superblock scheduling extracts ILP from frequently executed traces. This paper describes an effort to employ both software pipelining...

This paper presents the implementation of the compiler technique register pipelining with respect to energy optimization and its comparison against performance optimization. Generally, programs optimized for performance are also energy optimized. An exception to this rule is shown where the use of register pipelining improves the energy consumption by 17% while bringing down performance by 8.8%...

This paper introduces a new class of Huffman decoders which is a developmet of the parallel Huffman decoder model. With pipelining and partitioning, a regular architecture with an arbitrary degree of pipelining is developed. The proposed architecture dramatically reduces the symbol decoder requirements compared to previous results, and still is the actual implementation of the symbol decoder no...

In this paper, the matrix lookahead transformation is developed to achieve ne-grain pipelining for Cordic based QRD-RLS adaptive ltering algorithm. Various implementation styles are proposed. They include pipelining, block processing, and incremental block processing. The proposed architectures can operate at arbitrarily high sample rates, and consist of only Givens and a few Gaussian rotations...

The paper presents Gate Transfer Level (GTL) as a general framework for synthesis of industrial complexity asynchronous quasi-delay-insensitive (QDI) circuits. The GTL flow automatically provides the finest degree of pipelining (gate-level) resulting in extremely high-performance designs. Automatic gate level pipelining is not possible for synchronous design due to the stage balance problem and...

This paper presents a new concurrent multiplethreaded architectural model, called superthreading, f o r exploiting thread-level parallelism o n a processor. This architectural model adopts a thread pipelining execut ion model that allows threads with data dependences and control dependences to be executed in parallel. The basic idea of thread pipelining i s t o compute and forward recurrence da...

This paper presents a hardware-software partitioning algorithm that exploits a loop pipelining technique. The partitioning algorithm is based on iterative improvement. The algorithm tries to minimize hardware cost through hardware sharing and hardware implementation selection without violating given performance constraint. The proposed loop pipelining technique, which is an adaptation of a comp...