Packet switching in connection-oriented networks that may have multiple parallel links between pairs of switches is considered. An e cient packet-scheduling algorithm that guarantees a deterministic quality of service to connections with real-time constraints is proposed { this algorithm is a generalization of some recent multiprocessor scheduling algorithms, and o ers realtime performance guar...

Hybrid Si/SiC switches constituting a parallel connection of lower current rated SiC MOSFET and higher Si IGBT are becoming very attractive solution for designing high frequency high-power density power electronic converters. Due to the complementary nature devices (smaller inverter cost smaller conduction loss) switching loss junction temperature capability), these novel switch device configur...

"H"-like organic nanowire heterojunctions with two parallel 2-acetyl-6-dimethylamino-naphthalene wires vertically bridged by one 2,4,5-triphenylimidazole wire are prepared via cooperative molecular assembly in liquid phase. The exciton conversion at the junction interfaces is beneficial for the design of multichannel light-controlled photo-switches. The results provide better understanding of m...

We present an active switch architecture to improve the performance of systems connected via system area networks. Our programmable active switches not only flexibly route packets between any combination of hosts and I/O devices, but also have the capability of running application-level code, forming a parallel processor in the SAN subsystem. By replacing existing SAN-based switches with a new ...

Degradation and failure due to dielec been a dominant and pervasive reliability concer switches. Traditionally, the operational lifetime degradation phenomenon is extrapolated fr measurements of time-dependent shifts in Cap (C-V) characteristics under accelerated stress co paper, we explain why the classical large-signal may lead to a pessimistic under-prediction o Using both simulations and ex...

High bandwidth and low latency switches are commercially available. Using these switches, it has become a popular and cost-eeective way to interconnect workstations and processor clusters together as a parallel computing platform. The interconnection topology is usually irregular. On such systems, multicast is an important collective operation. Two steps are involved in a multicast: (1) the sou...

The demand for broadband communication is becoming more and more urging. In order to achieve a successful expand of the ATM technology, performance evaluation of large networks is a mandatory step and the challenge is now to simulate them in one piece. Distributed simulation is a promising tool for the simulation of such systems that can not be handled sequentially anymore. This paper presents ...

A method for fast time-domain simulation of piecewise-linear networks with switches is described in this paper. The method is based on a discrete-time switch model that consists of a constant conductance in parallel with a current source. In each simulation step, value of the current source is updated as a function of known network signals. The function takes one of two forms, depending on the ...

We describe an FPGA-based datacenter network simulator for researchers to rapidly experiment with O(10,000) node datacenter network architectures. Our simulation approach configures the FPGA hardware to implement abstract models of key datacenter building blocks, including all levels of switches and servers. We model servers using a complete SPARC v8 ISA implementation, enabling each node to ru...

This paper presents a new cascaded multilevel inverter topology in asymmetric configuration. Initially general topology is presented and then extended for higher number of stages. In this paper a new cascade diagonal dc source multilevel inverter topology is proposed, which included the increased number of output voltage levels with minimum number of switches as well as with minimum dc voltage ...