This paper studies the effect of high performance pipelined GF(2 256 ) bit-serial multiplier on elliptic curve point operations. A 3-stage pipelined version of the Massy-Omura GF(2 m ) normal basis multiplier for 160 ≤ m ≤ 256 was studied in terms of area overhead and throughput improvement. Simple gate area and delay models were used to estimate the throughput of the pipelined and the non-pipe...

This paper presents a merged multiplyaccumulate (MAC) hardware that is based on the modified Booth algorithm. The carry-save method is used in the Booth encoder, the Booth multiplier, and the accumulator sections to guarantee the fastest possible. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Also, the proposed ...

We consider convex quadratic programs with large numbers of constraints. We distribute these constraints among several parallel processors and modify the objective function for each of these subproblems with Lagrange multiplier information from the other processors. New Lagrange multiplier information is aggregated in a master processor and the whole process is repeated. Linear convergence is e...

In this paper, we present a low complexity bit-parallel Montgomery multiplier for GF(2m) generated with a special class of irreducible pentanomials xm + xm−1 + xk + x + 1. Based on a combination of generalized polynomial basis (GPB) squarer and a newly proposed square-based divide and conquer approach, we can partition field multiplications into a composition of sub-polynomial multiplications a...

This paper presents a low complexity architecture for a linear periodically time varying (LPTV) filter. This architecture is based on multi-input multi-output(MIMO) representation of LPTV filters. The input signal is divided into blocks and parallel processing is incorporated, there by considerably reducing the effective input sampling rate. A single multiplier can be shared for each linear tim...

Modulo multiplication plays an important role in the Fermat number transform and residue number systems; the diminished-1 representation of numbers has been found most suitable for representing the elements of the rings. Existing algorithms for modulo multiplication either use recursive modulo addition, or a regular binary multiplication integrated with the modulo reduction operation. Although ...

New VLSI circuit architectures for addition and multiplication modulo (2 1) and (2 + 1) are proposed that allow the implementation of highly efficient combinational and pipelined circuits for modular arithmetic. It is shown that the parallel-prefix adder architecture is well suited to realize fast end-around-carry adders used for modulo addition. Existing modulo multiplier architectures are imp...

This paper presents the design of a new multiplier architecture for normal integer multiplication of positive and negative numbers. It has been developed to increase the performance of algorithms for cryptographic and signal processing applications on implementations of the Instruction Systolic Array (ISA) parallel computer model [6,7]. The multiplier operates least significant bit (LSB)-first....

This paper presents a merged multiplyaccumulate (MAC) hardware that is based on the modified Booth algorithm. The carry-save method is used in the Booth encoder, the Booth multiplier, and the accumulator sections to guarantee the fastest possible. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Also, the proposed ...

This work proposes a processor architecture for elliptic curves cryptosystems over fields GF (2 m). This is a scalable architecture in terms of area and speed that exploits the abilities of reconfigurable hardware to deliver optimized circuitry for different elliptic curves and finite fields. The main features of this architecture are the use of an optimized bit-parallel squarer, a digit-serial...