We present HoneyTech, a tool for automatic synthesis of hybrid controllers. HoneyTech is an extension of the HyTech tool, with added features for linear hybrid automata region modeling and analysis. The tool has also been enhanced to improve performance by reducing the number of redundant operations during region computations. The tool has been used to implement the Wong-Toi hybrid controller s...

This paper describes a low noise variable gain amplifier (LNA) and a mixer for a WCDMA frontend receiver based on a direct architecture in 0.18-μm CMOS. The LNA provides a 50Ω input impedance and utilizes a tuned load to provide high selectivity. The LNA achieves a maximum small signal gain of 16.8 dB and a minimum gain of 4.6 dB with good input return loss. In the high gain and the low gain mo...

A low-noise amplifier (LNA) and mixer circuit in 0.35m CMOS operates at 2.1 GHz. Merging the LNA and mixer lowers the number of transistors in the signal path and thereby also the nonlinearity and power consumption. The circuit meets the specifications for a direct conversion wide-band code-division multiple access (WCDMA) receiver. Its noise figure is 3.4 dB (5 kHz to 5 MHz), the total convers...

This paper presents the design, implementation and measurements of a BiCMOS integrated tunable Low Noise Amplifier for 5 GHz WLAN applications. It consists of a cascode gain cell, noise and power matched to a 50 Ω input source, and power matched to a 50 Ω load. In order to broaden the available bandwidth, the output matching network is modified by means of a shunt varactor, thus allowing the tu...

This paper represents a 3.5 GHz narrow band differential LNA novel design for the improvement and reliability in 180μm CMOS technology. A 3.5 GHz proposed LNA designed structure is a fully integrated 3GHz high gain narrow band LNA by using differential cascode technique with modified inductive degenerated topology. The low power high gain, less noise, CMOS LNA is designed for wimax applications...

Second-harmonic control is implemented in a balanced common-emitter configuration to facilitate frequency-independent third-order intermodulation distortion cancellation. Moreover, this circuit configuration facilitates a simultaneous match for either power and linearity or noise and linearity. Experiments demonstrated an improvement of over 15 dB in the output third-order intercept point while...

Abstrac—Second-harmonic control is implemented in a balanced common-emitter configuration to facilitate frequency independent third–order intermodulation distortion (IM3) cancellation. Experiments demonstrated an over 15 dB improvement in the output third-order intercept point (OIP3).

A low-power 435-MHz single-ended low-noise amplifier was implemented in a 0.35-μm silicon on insulator (SOI) CMOS technology. The SOI CMOS LNA has a simulated noise figure of 0.6 dB, input 1-dB compression point of –12.5 dBm, input thirdorder intercept point of –5 dBm, and small-signal gain of 22 dB. Total power dissipation is 10 mW from a 2.5-V supply. LNA chip area is 1.4 mm x 0.58 mm. Due to...