With the emergence of the packet-switched networks as a possible system-on-chip (SoC) communication paradigm, the design of network-on-chips (NoC) has provided a challenge to the designers. Meeting latency requirements of communication among various cores is one of the crucial objectives for system designers. The core interface to the networking logic and the communication network are the key c...

Congestion in on-chip networks may cause many drawbacks in multiprocessor systems including throughput reduction, increase in latency, and additional power consumption. Furthermore, conventional congestion control methods, employed for on-chip networks, cannot efficiently collect congestion information and distribute them over the on-chip network. In this paper, we present an on-chip network ar...

A conventional Network-on-Chip (NoC) router uses input buffers to store packets to improve performance, but consume significant power. While bufferless NoC design has shown reduction in area and power, and offers similar performance to conventional buffered designs for many workloads, than conventional buffered routers at high network load. This degradation is a significant problem for widespre...

This paper proposes a new methodology to design of coarse-grained routers in order to improve performance of Networks-on-Chip (NOC). In this approach, several cluster routers in region area of K×K are grouped into one new router called K2Router with similar cost of area and power, however, the performance of whole network is improved. The proposed routers are general in terms of constructions a...

On-chip optical clock distribution is being investigated as a fbture means to increase clock speed and reduce clock power. While extremely small skew in the arrival of an on-chip optical signal can be achieved, the conversion of the optical signal to a local electrical clock may be subject to substantial variation. A baseline receiver circuit has been designed and fabricated. We find that sensi...

Abstract— The wavelength routed optical network (WRON) is a promising optical interconnection architecture that can be integrated into a System-on-Chip (SoC) with an intention to replace traditional wire-connected on-chip micro-networks which pose severe bandwidth limitations on future super large SoC chips. In this paper, we present a new recursive architecture, the Recursive Wavelength Routed...

The design of recent Systems-on-Chip (SoC) for a large scope of applications, such as telecom and multi-media domains, and in various platform types ranging from dedicated platforms to fully programmable platforms, is mainly constrained by communications. Networks-on-Chip (NoC) have recently emerged as a promising concept to support communication on SoCs providing a solution to connect differen...

Optical Network on Chip (ONoC) architecture is emerging as a promising candidate in multiprocessor systems-on-chip (MPSoC) because of ultrahigh communication bandwidth, low latency and power consumption. The topology and layout of ONoC has a great impact on the network performance. Waveguide crossing in the topology would influence power consumption and crosstalk noise, which could influence th...