In this paper, we present an investigation into the challenges in designing a network processor that is additionally capable of security processing. First, we provide an overview of the cryptographic algorithms utilized in security processing and highlight several current network protocols that employ these algorithms. Second, we discuss several issues in designing a solution for security proce...

Packaging constraints motivate a two-level interconnection network for a multiprocessor. A single node in the global network contains multiple processors connected by a local network. An important issue in two-level networks is how alternative numbers of processors per node changes the per link traac in the global network. In the case of a hypercube global network we consider three communicatio...

Network Processors are a recent development targeted at the high-end network switch/router market. They usually consist of a large number of processing cores, multi-threaded in hardware, that are specialized in analysing and altering frames arriving from the network. For this purpose there are hardware co-processors to speed-up e.g. tree-lookups, checksum calculations etc. The usual application...

In this paper, we study the problem of scheduling parallel loops at compile time for a heterogeneous network of workstations. We consider heterogeneity in various aspects of parallel programming: program, processor, memory and network. A heterogeneous program has parallel loops with different amounts of work being done in each iteration; heterogeneous processors have different speeds; heterogen...

In this paper, we study the problem of scheduling parallel loops at compile-time for a heterogeneous network of workstations. We consider heterogeneity in various aspects of parallel programming: program, processor, memory and network. A heterogeneous program has parallel loops with diierent amount of work in each iteration; heterogeneous processors have diierent speeds; heterogeneous memory re...

Programable Network Processors(NPUs) are embedded system-on-chip multiprocessors optimized for packet processing and forwarding tasks at line speeds. To meet the demands of increasing data rates and complex network applications, current architectures of NPUs are implemented with several embedded processor cores (or microengines) to induce parallelism in packet processing tasks. In this paper we...

We characterize exactly the cases in which it is possible to elect a leader in an anonymous network of processors by a deterministic algorithm, and we show that for every network there is a weak election algorithm (i.e., if election is impossible all processors detect this fact in a distributed way).

A distributed program is presented that ensures delivery of a message to the functioning processors in a computer network, despite the fact that processors may fail at any time. All processor failures are assumed to be detected and to result in halting the offending processor. A reliable communications network is assumed.

A new concept of parallel architecture for image processing is presented in this paper. Named LAPMAM (Linear array processors with Multi-mode Access Memory), this architecture, for a 512 x 512 image, has 512 processors and four memory planes each of 5122 memory modules. One important characteristic of this architecture is its memories modules that allow different access modes: RAM, FIFO, normal...

ÐThe goal of the fault diagnosis agreement (FDA) problem is to make each fault-free processor detect/locate a common set of faulty processors. The problem is examined on processors with mixed fault model (also referred to as hybrid fault model). An evidence-based fault diagnosis protocol is proposed to solve the FDA problem. The proposed protocol first collects the messages which have accumulat...