Communication has always been a limiting factor in making efficient computing architectures with large processor counts. Reconfigurable interconnects can help in this respect, since they can adapt the interprocessor network to the changing communication requirements imposed by the running application. In this paper, we present a performance evaluation of these reconfigurable interconnection net...

Due to advances in fiber-optics and VLSI technology, interconnection networks which allow multiple simultaneous broadcasts are becoming feasible. In such large systems, hot-spot contention can occur when several processing nodes concurrently request access to one data structure with resulting severe performance degradation. This paper presents one broadcast architecture, called the SOME-Bus int...

Modern embedded devices require high performances such as computing, throughput and power consumption. Multiprocessor System-on-Chip (MPSoC) is a promising solution to meet the requirements. And the Network-on-Chip (NoC) is used as the interconnection of MPSoC. Whereas it brings more challenge on application programming and fast design exploration of software and hardware implements automatical...

Total exchange (or multiscattering) is one of the important collective communication problems in multiprocessor interconnection networks. It involves the dissemination of distinct messages from every node to every other node. We present a novel theory for solving the problem in any multidimensional (cartesian product) network. These networks have been adopted as cost-eeective interconnection st...

We compare two types of multiprocessor interconnection networks, fat trees and express cubes. Sample networks of each type were designed using realistic hardware constraints. We model different communication patterns on them and compute metrics such as average hop count, average latency, and bisection bandwidth, and show approximate costs for each network in terms of router and wire counts. Res...

This paper aims to explore an alternative planar layout of the Data Vortex optical network. It is desirable to provide high throughput and low latency information exchange between processors or Input/ Output (I/O) ports within advanced multiprocessor computing and communication systems. Optical interconnection networks can overcome many limits in electrical interconnection networks and provide ...

In vector multiprocessor systems, collisions in the interconnection network and conflicts in the memory modules are the main causes of the performance degradation. In this work we propose to synchronize the access to the memory system so that streams can be accessed with the minimum achievable latency if their elements are requested out of order. The mechanism uses a blockinterleaved storage sc...

The omega network has various attractive topological properties. It supports both one-to-one message routing and broadcast routing. Independent of the system size, every node in the network has a fixed size; therefore, it is used intensively in large-sized systems. In this paper, we examine a reliable omega-based multiprocessor system that preserves its full rigid omega configuration even in th...

The design of space systems capable of performing realtime Synthetic Aperture Radar (SAR) is a significant challenge in HPEC due to the high processor, memory, and network requirements imposed by SAR. However, building a system to support SAR and other Space-Based Radar (SBR) algorithms simultaneously is an even greater challenge. This presentation describes simulation results from a SAR applic...

The increasing complexity of present SoCs demands new, scalable, reusable, parallel interconnection models for their cores. This paper presents a comparison study made in an on chip reconfigurable multiprocessor, the X4CP32, on its interconnection. Three models were proposed, a bus system, a SoC using FIFO buffering, and a SoC using SAFC buffering. All the models were described in SystemC and s...