A novel ultra-high compliance, low power, very accurate and high output impedance current output stage (COS) with extremely high output current drive capability is proposed in this paper. The principle of operation of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by HSPICE simulation in TSMC 0.18µm CMOS, BSIM3, and Level4...

A continuous-time (CT) ΣΔ modulator for sensing and direct analog-to-digital conversion of nA-range (subthreshold) currents is presented in this work. The presented modulator uses a subthreshold technique based on subthreshold source-coupled logic cells to efficiently convert subthreshold current to digital code without performing current-to-voltage conversion. As a benefit of this technique, t...

This paper proposes a simple carrier based Hybrid active zero state pulse width modulation (HAZSPWM) Algorithm (HPWM) which is capable of reducing the common mode voltage produced by the Pulsewidth Modulation (PWM) Inverter fed vector controlled induction motor drive. The classical vector controlled algorithm gives variable switching frequency operation and increased harmonic distortion due to ...

A scheme for a three-level voltage space phasor generation with common-mode voltage elimination is proposed. An open-end-winding induction motor, fed from both ends by two threelevel inverters, which are realised by a cascading two two-level inverter, is used in this configuration. The voltage space vectors of individual three-level inverters, which generate the same commonmode voltage in the i...

After giving a summary of investigated passive and active schemes to mitigate common mode problems a modeling approach for the common mode voltage (CM voltage) is presented for three-level rectifiers. A novel Active Commonmode Voltage Cancellation (ACC) scheme is proposed, utilizing the reconstructed CM voltage to derive a simpler driving scheme as presented by previous contributions. The ACC s...

This paper presents a resilient cache memory for dynamic variation tolerance in a 40-nm CMOS. The cache can perform sustained operations under a large-amplitude voltage droop. To realize sustained operation, the resilient cache exploit 7T/14T bit-enhancing SRAM and on-chip voltage/temperature monitoring circuit. 7T/14T bitenhancing SRAM can reconfigure itself dynamically to a reliable bit-enhan...

The continuous scaling down of technology, there is the exponential increase in leakage current. The MTCMOS is an attractive design to reduce the leakage current in idle state. Sleep-to-Active mode transition is an important concern in MTCMOS circuit because it produces ground bounce noise. In this paper, Threshold Voltage tuning method with MTCMOS circuit is used to reduce the ground bounce no...

A second order voltage mode tunable universal filter is presented. The voltage mode filter is based on dual output second generation current controlled current conveyor (DOCCCII). The filter is capable of realizing high pass (HP), low pass (LP), band pass (BP), notch pass (NP) and all pass (AP) responses in voltage mode (VM). The filter employs only two capacitors and hence enjoys minimum compo...

This paper presents a nonlinear analytical model for micromechanical silicon ring resonators with bulk-mode vibrations. A distributed element model has been developed to describe the dynamic behavior of the micromechanical ring resonator. This model shows the nonlinear effects in a silicon ring resonator focusing on the effect of large amplitudes around the resonance frequency, material and ele...

This paper presents the design and a new low-cost process for fabrication of a second-order micromechanical filter using UV-LIGA technology. The micromechanical filter consists of two identical bulk-mode ring resonators, mechanically coupled by a flexural-mode beam. A new lumped modeling approach is presented for the bulk-mode ring resonators and filter. The validity of the analytical derivatio...