An advanced substrate level patterning technique is presented to realize 3D interconnection circuitry on electronic modules. The technique is based on diffraction of light by phase gratings. The phase gratings are incorporated into the photomask at discrete locations. By illuminating the photomask at normal incidence, the phase grating causes locally inclined UV exposure, which is used to expos...

Published by the IEEE Computer Society 0018-9162/11/$26.00 © 2011 IEEE For many computer architects, the first challenge takes priority. After all, we are used to operating under the protection of well-designed abstractions that permit our architectures to accommodate anything from ideal switches to the least palatable of devices that might be foisted upon us. However, the nanodevices that prev...

This paper describes the microelectronic design education initiatives sponsored by the Pittsburgh Digital Greenhouse. These programs were created to support a growing regional cluster of microelectronic system design companies. Both resident instruction and continuing education initiatives are described, and progress to date is highlighted.

Recent advances in the design and fabrication techniques of microelectronic devices have resulted in tremendous improvements in system functionality, performance and power consumption. These improvements have been fueled by tremendous growth in the semiconductor industry and increasing demand for hand-held and wireless electronic systems. However, these same advances also impact the stability, ...

ÐThe traditional goals of the floorplanning process for a new integrated circuit have been minimizing the total chip area and reducing the routing cost, i.e., the total length of the interconnecting wires. Recently, it has been shown that, for certain types of chips, the floorplan can affect the yield of the chip as well. Consequently, it becomes desirable to consider the expected yield, in add...

We present a timing driven oorplanning program for general cell layouts. The approach used combines quality of force directed approach with that of constraint graph approach. A oorplan solution is produced in two steps. First a timing and connectivity driven topological arrangement is obtained using a force directed approach. In the second step, the topological arrangement is transformed into a...

Microelectronics teaching content is extremely wide and diverse, rich in different types of devices, circuits and systems, layers of abstraction, and design tradeoffs. We propose to use Featureion, and design tradeoffs. We propose to use Feature Diagrams for specification and structuring of microelectronics teaching content at different layers of abstraction starting from organization of teachi...