In modern computing systems there is the need to utilize a large amount of data in maintaining high efficiency. Limited memory bandwidth, coupled with performance gap between and logic, impacts heavily on algorithms performance, increasing overall time energy required for computation. A possible approach overcome such limitations Logic-In-Memory (LIM). this paper, we propose LIM architecture ba...

We propose an area-efficient high-speed interleaved Viterbi decoder architecture, which is based on the state-parallel architecture with register exchange path memory structure, for interleaved convolutional code. The state-parallel architecture uses as many add-compare-select (ACS) units as the number of trellis states. By replacing each delay (or storage) element in state metrics memory (or p...

We propose a secondary cache architecture that combines a predictive fetch strategy with a distributed cache to build a high performance memory system. The cache is partitioned into smaller units and distributed evenly in the main memory space. The architecture offers high bandwidth between the cache and the DRAM memory. A hardware prediction scheme is used to prefetch data into the cache and h...

Traditional improvements in packet switch architecture aimed at increasing switch performance in terms of utilization, fairness and QoS. This paper focuses on improving architecture to achieve implementation feasibility of terabit aggregate data rates while maintaining such performance. Terabit class shared-memory switch chips are simple in concept but are a challenge to build due to the memory...

DICE is a shared-bus multiprocessor based on a distributed shared-memory architecture, known as Cache-Only Memory Architecture (COMA). Unlike previous COMA proposals for large-scale multiprocessing, DICE utilizes the COMA to effectively decrease the gap between modern high-performance microprocessors and the bus. As microprocessors become faster and demand more bandwidth, the already limited sc...

Hierarchical block matching is an eecient motion estimation technique which provides an adaptation of the block size and the search area to the properties of the image. In this work, we propose two novel special-purpose architec-tures for implementing hierarchical block matching. The rst architecture is memory-eecient, but requires a large external memory bandwidth and a large number of process...

Triangles are the basic substructure of networks and triangle counting (TC) has been a fundamental graph computing problem in numerous fields such as social network analysis. Nevertheless, like other problems, due to high memory-computation ratio random memory access pattern, TC involves large amount data transfers thus suffers from bandwidth bottleneck traditional Von-Neumann architecture. To ...