A test pattern generator generates a pseudorandom that can be weighted to reduce the fault coverage in built-in self-test. The objective of this paper is propose new TPG for scan-based BIST architecture. motivation work generate efficient patterns enabling scan chains with reduced power consumption and area. Additionally, pseudo-primary seed maximized obtain considerable length patterns. maximu...

While high-quality BIST (Built-In Self Test) based on deterministic vectors often has a prohibitive cost, pseudorandom based BIST may lead to low DC (Defects Coverage) values, requiring however very long test sequences with the corresponding energy waste and possible overheating due to extra switching activity caused by test vectors. The purpose of this paper is to discuss how a recently propos...

QUANTIZATION STRATEGIES FOR LOW-POWER COMMUNICATIONS

-------------------------------------------ABSTRACT---------------------------------------In this paper, a new design of wireless sensor network (WSN) node is discussed which is based on components with ultra low power. We have developed a Low cost and low power WSN Node using MSP430 and nRF24L01. The architectural circuit details are presented. This architecture fulfils the requirements like l...

In recent years, with fast growth of mobile communication and portable computing systems, design for low power has become the challenge in the field of Digital VLSI design. The main focus of the paper is to make a comparative study of low power Linear Feedback Shift Register (LFSR) architecture such as Built In Self Test (BIST), it has been often seen that during test mode process the power con...

Energy neutral operation of WSNs can be achieved by exploiting the idleness of the workload to bring the average power consumption of each node below the harvesting power available. This paper proposes a combination of state-of-the-art low-power design techniques to minimize the local and global impact of the two main activities of each node: sampling and communication. Dynamic power management...

Test power is major issue of recent scenario of VLSI testing. There are many test pattern generation techniques for testing of combinational circuits with different tradeoffs. The don’t care bit filling method can be used for effective test data compression as well as reduction in scan power. This paper gives a new advancement in automatic test pattern generation method by feeling don’t care bi...