We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple Macintosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C ...

Preliminary -The BERTScope BSX-series Bit Error Rate Tester introduces a receiver test platform capable of supporting emerging Gen4 standards and beyond. With the addition of powerful data processing and internal Tx equalization, the BERTScope supports protocol-based handshaking and synchronization with your device under test (DUT), including interactive link training at data rates up to 32 Gb/...

Key performance specifications Up to 1.6 Gb/s Pattern Generator/Error detector for fast, accurate characterization of digital communications signaling systems PRBS or 8 Mb user-defined patterns provide the versatility to debug or verify any combination of digital signaling ANSI jitter measurements (RJ, DJ, and TJ) to measure the impact of random and deterministic jitter on the total jitter at B...

Die Aufgaben, die ein Software-Tester zu erledigen hat, gehören bei vielen in der Softwareproduktion tätigen Personen zu den weniger attraktiven. Testen wird oft noch als notwendiges Übel am Ende der Softwareerstellung angesehen. Das Berufsbild des Testers ist nicht sehr angesehen und wird von den meisten nicht angestrebt. Diese Sichtweise steht allerdings im krassen Widerspruch zur Bedeutung d...

We present an adaptive tester for the unateness property of Boolean functions. Given a function f : {0, 1}n → {0, 1} the tester makes O(n log(n)/ε) adaptive queries to the function. The tester always accepts a unate function, and rejects with probability at least 0.9 if a function is ε-far from being unate.

We are investigating on-line model-based test generation from non-deterministic output-observable Input/Output Extended Finite State Machine (I/O EFSM) models of Systems Under Test (SUTs). We propose a novel constraint-based heuristic approach (Heuristic Reactive Planning Tester (χRPT)) for on-line conformance testing non-deterministic SUTs. An indicative feature of χRPT is the capability of ma...