In the renewable energy sources, PV system forms the reliable for power generation. Thus the transformerless CMI is considered to be the best alternative for low cost and high efficiency photovoltaic systems. Eliminating the leakage current is one of the most important issues for transformerless inverters in grid-connected photovoltaic system applications, where the technical challenge is how t...

In this paper, a new domino circuit is proposed with low leakage current and high noise immunity which decreases the parasitic capacitance on the dynamic node. This yields a smaller keeper transistors for wide fan-in gates to implement fast and robust circuits. The technique utilized is based on comparison of mirrored current of the pull-up network with its worst case leakage current. Thus, the...

Multilevel inverters are a source of high power, often used in medium-voltage application. Multilevel converters have received increased interest recently due to high quality output waveform and decrease the harmonic distortion in the output waveform without decreasing the inverter power output. A multilevel inverter uses a series of semiconductor power converters, thus generating higher voltag...

Pre-breakdown (leakage) and breakdown currents and photon-emission associated with the currents, under impulse (0.36!10 IJ-S) voltage stress, along high purity (p>30 KQ em) silicon, with and without gold end contacts in vacuum (-lQ-6 Torr), are discussed. Three distinct phases leading to the breakdown condition are observed. These are one-carrier (hole) leakage current, two-carrier (electrons a...

An ultra-low-leakage power-rail ESD clamp circuit, composed of the SCR device and new ESD detection circuit, has been proposed with consideration of gate current to reduce the standby leakage current. By controlling the gate current of the devices in the ESD detection circuit under a specified bias condition, the whole power-rail ESD clamp circuit can achieve an ultra-low standby leakage curren...

In this paper, gate leakage current has been mitigated by the use of novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure for the first time. A compact analytical model has been developed to study the gate leakage behaviour of proposed MOSFET structure. The result obtained has found good agreement with the Sentaurus Simulation. Fringing gate electric field...

Direct tunneling current through the gate oxide is becoming a significant component of transistor leakage in deep sub-micron technology. This paper studies how gate leakage impacts the performance of analog CMOS ICs for the 90nm node. Results show that in DC referencing circuits such as current mirrors, a tradeoff exists between transistor width and mirrored reference current to improve accurac...

A voltage scalable 0.26 V, 64 kb 8T SRAM with 512 cells per bitline is implemented in a 130 nm CMOS process. Utilization of the reverse short channel effect in a SRAM cell design improves cell write margin and read performance without the aid of peripheral circuits. A marginal bitline leakage compensation (MBLC) scheme compensates for the bitline leakage current which becomes comparable to a re...