We introduce the class of Interrupt Timed Automata (ITA), a subclass of hybrid automata well suited to the description of timed multi-task systems with interruptions in a single processor environment. While the reachability problem is undecidable for hybrid automata we show that it is decidable for ITA. More precisely we prove that the untimed language of an ITA is regular, by building a finite...

Experimental data indicate that norepinephrine is critically involved in aspects of vigilance and attention. Previously, we considered the function of this neuromodulatory system on a time scale of minutes and longer, and suggested that it signals global uncertainty arising from gross changes in environmental contingencies. However, norepinephrine is also known to be activated phasically by fam...

We study the minimum number of interrupts in an optimal time-slot assignment of a time-division multiple-access (fDMA) system. If the number of channels c in the TDMA system equals 2, then there always exists an optimal assignment with at most one interrupt. If c ~ 3, then there exist TDMA systems for which each optimal assignment requires at least (c-l)(c 2) interrupts.

We examine interruptions in a corpus of spontaneous taskoriented dialogue. We present evidence that interruptions occur at particular places in conversation. They are likely to occur during or after speech with certain acoustic/prosodic properties. We also examine the speech of interruptions themselves and find a number of significant differences between interrupting and non-interrupting turns.

This paper presents the design and FPGA implementation of a 32bit configurable micro controller. The micro controller contains a 32-bit processor based on RISC-V Instruction Set Architecture, Cache memories, interrupt support, multiplexed buses and a Debug Unit. The processor support all integer arithmetic. Cache memories have various sizes upto 16kB. Prioritized stacked interrupt control is pr...

Title of Thesis: In-line Interrupt Handling and Lockup Free TLBs Degree Candidate: Aamer Jaleel Degree and Year: Master of Science, 2002 Thesis directed by: Dr. Bruce L. Jacob Department of Electrical and Computer Engineering The effects of the general-purpose precise interrupt mechanisms in use for the past few decades have received very little attention. When modern out-of-order processors ha...

The work was carried out in four major stages. The first stage was to port the Chorus kernel on the Macintosh hardware. In the second stage we changed the way Chorus managed the hardware in order to keep the MacOS system alive. Conversely, we modified slightly the way Chorus was booted so as to present it as an application to MacOS. This led us to the third stage, which was to share system even...