In August 2020, Intel asked the research community for feedback on newly offered architecture extensions, called Trust Domain Extensions (TDX), which give more control to Domains (TDs) over processor resources. One of key features these extensions is remote attestation mechanism, provides a unified report verification mechanism TDX and its predecessor Software Guard (SGX). Based our experience ...

This thesis investigates on changes in semiconductor industry's product development methodology by following Intel's product development from year 2000. Intel was challenged by customer's preference change, competitors new enhanced product, internet bubble burst economy, and miss steps in the business strategy. Dynamics of these challenges drove Intel to develop a new product strategy: Tick-Toc...

Genetic information is increasing exponentially, doubling every 18 months. Analyzing this information within a reasonable amount of time requires parallel computing resources. While considerable research has addressed DNA analysis using GPUs, so far not much attention has been paid to the Intel Xeon Phi coprocessor. In this paper we present an algorithm for large-scale DNA analysis that exploit...

Hyper-Threading Technology delivers significantly improved architectural performance at a lower-thantraditional power consumption and die size cost. However, increased logic complexity is one of the trade-offs of this technology. Hyper-Threading Technology exponentially increases the micro-architectural state space, decreases validation controllability, and creates a number of new and interesti...

Intel Corporation set itself a goal to reduce its global-warming greenhouse gas footprint by 20% by 2012 from 2007 levels. Through the use of sustainable IT, the Intel IT organization is recognized as a significant contributor to the company’s sustainability strategy by transforming its IT operations and overall Intel operations. This article describes how Intel has achieved IT sustainability b...

The Intel® Xeon PhiTM coprocessor platform enables offload of computation from a host processor to a coprocessor that is a fully-functional Intel® Architecture CPU. This paper presents the C/C++ and Fortran compiler offload runtime for that coprocessor. The paper addresses why offload to a coprocessor is useful, how it is specified, and what the conditions for the profitability of offload are. ...

In these years, computerization has been more and more important in the financial area. The computational intensity and realtime constraints of those financial models require high-throughput parallel architectures. In this paper, optimization of widely-used binomial option pricing model has been implemented on the worlds largest supercomputer, Tianhe-2. In our work, we employ several optimizing...

This technical report gives detail on the results obtained from testing of the ASUS P5LD2-VM Motherboard with Intel network interface cards (Intel 10/100 and Onboard Intel PRO/1000 PCI Express) for time stamping accuracy. The hardware is tested for the purposes of being a Flow Meter in our prototype ANGEL QoS architecture. A number of affecting factors have been investigated, including the link...