This paper describes a VHDL implementation of a behavioural model for novel programmable resolution analog to digital converters (ADCs). This architecture uses the dichotomic method in the conversion. The goal for using this VHDL description is to validate the algorithm conversion and facilitate the synthesis of the digital part. In this example it includes digital control of dichotomic method....

Error modelling has played a major role in generating post-corrections of analogue to digital converters (ADC). Benefits by using parametric models for post-correction are that they requires less memory and that they are easier to identify for arbitrary signals. However, the parameters are estimated in two steps; firstly, the integral nonlinearity (INL) is estimated and secondly, the model para...

Fast Analog Signal Processor FASP-0.1 [1, 2] is a prototype ASIC designed at NIPNE for HCR-TRD having in mind the CBM experiment at FAIR. In this contribution we report on relevant measured parameters of ASIC analog channels and a FEE based on FASP, designed and built for in-beam tests of our HCR-TRD prototypes [3]. ASIC measured parameters [4, 5] Quiescent supply current (VD = 3.3V): 30mA ±1mA...