This paper presents a high-speed, low-power and low area encoder for implementation of flash ADCs. Key technique for design of this encoder is performed by convert the conventional 1-of-N thermometer code to 2-of-M codes (M = ¾ N). The proposed encoder is composed from two-stage; in the first stage, thermometer code are converted to 2-of-M codes by used 2-input AND and 4-i...

Adaptive algorithms lead to adjust the system coefficients based on the measured data. This paper presents a dichotomous coordinate descent method to reduce the computational complexity and to improve the tracking ability based on the variable forgetting factor when there are a lot of changes in the system. Vedic mathematics is used to implement the multiplier and the divider in the VFF equatio...

The purpose of this study is to provide a model with a dynamic system method to investigate the factors affecting the technological capabilities enhancement in the high-tech industries of high-speed train of the rail transportation system. For this purpose, after reviewing the literature and conducting several meetings with experts in the rail transportation industry, a conceptual and qualitati...

T SURPASS the speed limitations of more conventional approaches to printing digital infonnation, which commonly involve hard type faces coming in contact with the recording paper, some essentially nonmechanical methods have been investigated. The fundamental charflcteristic common to these systems is that character selection, positioning, and formation are accomplished without mechanical motion...

Abstract. High-speed MARS encryption/decryption hardware was developed using a 0.18μm IBM CMOS technology. In order to boost performance, a special adder and multiplier was designed by optimizing the adder block structure and interconnections between adder cells using signal delay profiles. A description of the hardware including block diagrams and data flow diagrams is presented. One of the mo...

Introduction Active notch filters have been used in the past for applications like elimination of 50and 60-Hz hum components. They have proven to be somewhat problematic from the standpoints of center frequency (f0) tuning, stability, and repeatability. The advent of high-speed amplifiers opens the possibility of higher-speed notch filters—but are they actually producible? This article will sho...

BERTIL SCHMIDT School of Computer Engineering Nanyang Technological University N4-02a-32 Nanyang Avenue SINGAPORE [email protected] MANFRED SCHIMMLER Institut für Datentechnik und Kommunikationsnetze Technische Universität Braunschweig Hans-Sommer-Str. 66, 38106 Braunschweig GERMANY [email protected] HEIKO SCHRÖDER School of Computer Science and IT RMIT University GPO Box 2476V Mel...

We studied the feasibility of estimating walking speed using a shank-mounted inertial measurement unit. Our approach took advantage of the inverted pendulum-like behavior of the stance leg during walking to identify a new method for dividing up walking into individual stride cycles and estimating the initial conditions for the direct integration of the accelerometer and gyroscope signals. To te...

The oxygen cost of transport per unit distance (CoT; mL·kg(-1)·km(-1)) shows a U-shaped curve as a function of walking speed (v), which includes a particular walking speed minimizing the CoT, so called economical speed (ES). The CoT-v relationship in running is approximately linear. These distinctive walking and running CoT-v relationships give an intersection between U-shaped and linear CoT re...

1.Problem of High-Speed Interface Macro Testing Because the function of the chip is guaranteed, the high-speed function test is important. Moreover, it is an important issue in LSI test how cheaply to do this test. The high-speed function test in an internal logical circuit can be tested by using BIST methodology and the output clock of PLL with a low-speed and low-cost ATE. However, the high-s...