In this study, we introduce a design of all-optical module for half-adder/half-subtracter and 2-to-4 decoder that generates simultaneously five of all-optical logic gates at 10 Gbps. These logic gates use dispersion compensation fiber (DCF) based on four-wave mixing (FWM). This design is integrated and economic. The various outputs can be manipulated by controlling nonlinear polarization rotati...

This paper presents a performance analysis of hybrid 1-bit full-adder circuit design. The adder cell is dissected into smaller modules. The modules are analyzed and calculated extensively. To explore good-drivability, noise-robustness, and low-energy operations for deep sub micrometer to explore hybrid-CMOS style design. Hybrid-CMOS design style uses various CMOS logic style circuits to constru...

In this paper, the various low power delay product full adder circuits have been analyzed. The adder is the fundamental blocks of any arithmetic circuit, so even a small reduction power or delay leads to improved performance of the circuit with optimal power saving. A 10T adder technique is the famous low power delay product full adder circuits with minimum transistor count. A new 10T technique...

In this paper, a proposed 1-bit hybrid full adder design employing both transmission gate logic and complementary metal– oxide–semiconductor (CMOS) logic is reported. The design is implemented for 1-bit Ripple Carry Adder and then is extended for 64-bit Ripple Carry Adder. The circuit is implemented using Mentor Graphics tools 130nm technology. The performance parameters such as delay, area, to...

A Neural Network, in general, is not considered to be a good solver of mathematical and binary arithmetic problems. However, networks have been developed for such problems as the XOR circuit. This paper presents a technique for the implementation of the Half-adder circuit using the CoActive Neuro-Fuzzy Inference System (CANFIS) Model and attempts to solve the problem using the NeuroSolutions 5 ...

A parallel adder which is optimal in both delay and size under left-to-right input arrival is proposed. The delay is the computation time after the arrival of the nal input bits. The proposed adder is composed of a carry select adder (CSA) and a small adder based on the on-they conversion (OTFA). Parallel computation in the CSA and the OTFA which make full use of the delay of the input arrival ...

The terahertz optical asymmetric demultiplexer (TOAD) or semiconductor amplifier (SOA)-assisted Sagnac switches have been used to construct an all-optical 4-bit carry skip adder. This design aims satisfy the high speed and accuracy requirements of modern ultrafast digital transmission. Using a combination multiplexer full adder, we describe When compared ripple adder look-ahead may be employed ...

moving towards nanometer scales, quantum-dot cellular automata (qca) technology emerged as a novel solution, which can be a suitable replacement for complementary metal-oxide-semiconductor (cmos) technology. the 3-input majority function and inverter gate are fundamental gates in the qca technology, which all logical functions are produced based on them. like cmos technology, making the basic c...

The Full Adder circuit is an important component in application such as Digital Signal Processing (DSP) architecture, microprocessor, and microcontroller and data processing units. This paper discusses the evolution of full adder circuits in terms of lesser power consumption, higher speed. Starting with the most conventional 28 transistor full adder and then gradually studied full adders consis...

Conservative and reversible logic gates are widely known to be compatible with revolutionary computing paradigms such as optical and quantum computing. A fundamental conservative reversible logic gate is the Fredkin gate. This paper presents efficient adder circuits based on the Fredkin gate. Novel full adder circuits using Fredkin gates are proposed which have lower hardware complexity than th...