The well-known classical constructions of garbled circuits use four ciphertexts per gate, although various methods have been proposed to reduce this cost. The best previously known methods for optimizing AND gates (two ciphertexts; Pinkas et al., ASIACRYPT 2009) and XOR gates (zero ciphertexts; Kolesnikov & Schneider, ICALP 2008) were incompatible, so most implementations used the best known me...

Transversal operations in quantum error correction, that is logical gates that are executed by applying a set of gates in parallel, are the most straightforward form of fault-tolerant quantum logic. Naturally, characterizing the set of logical gates that can be implemented transversally for a class of codes is of great importance to fault-tolerant quantum architectures. In this work, we classif...

In advancing beyond the von Neumann architecture, nanomagnetic logic offers an attractive approach to in-memory computation by exploiting energy hierarchy of coupled nanomagnets. However, low-power operation is largely incompatible with deterministic logic, because temperature required for fast reduces coupling too much. This study overcomes that problem using local, selective plasmon-assisted ...

background in spite of common usage of the inferior alveolar nerve block (ianb), this method has some well-defined restrictions. objectives the purpose of the present study was to compare these two techniques for the surgical removal of impacted lower third molars. patients and methods a total of 44 similarly impacted lower third molars (22 patients with two similar teeth) were selected. in eac...

This paper presents an automated procedure for the technology mapping of timed circuits to practical gate libraries. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the speciication which is used throughout the design process to optimize the implementation. Our procedure begins with a timed speciication and a delay-annotated gate library descr...