A systematic capacitance-voltage study has been performed on GaAs metal-oxide-semiconductor MOS structures with atomic-layer-deposited HfO2/Al2O3 nanolaminates as gate dielectrics. A HfO2/Al2O3 nanolaminate gate dielectric improves the GaAs MOS characteristics such as dielectric constant, breakdown voltage, and frequency dispersion. A possible origin for the widely observed larger frequency dis...

The realization of single-molecule electronic devices, in which a nanometer-scale molecule is connected to macroscopic leads, requires the reproducible production of highly ordered nanoscale gaps in which a molecule of interest is electrostatically coupled to nearby gate electrodes. Understanding how the moleculegate coupling depends on key parameters is crucial for the development of high-perf...

A recombination-controlled tunneling model is used to explain the strong frequency dispersion seen in the accumulation capacitance and conductance of dielectric/n-In0.53Ga0.47As metal-oxidesemiconductor capacitors. In this model, the parallel conductance is large when, at positive gate biases, the metal Fermi level lines up with a large density of interface states in the In0.53Ga0.47As band gap...

Sub-30 nm III-V planar Quantum-Well (QW) n-type MOSFETs are fabricated through a self-aligned CMOS compatible front-end process. Good performance and short-channel effect mitigation are obtained through the use of a QW-channel that incorporates a thin pure InAs subchannel and extremely scaled HfO2 gate dielectric on a very thin InP barrier (total barrier EOT<1 nm). The devices also feature self...

Over the last decade, field-effect transistors (FETs) with nanoscale dimensions have emerged as possible label-free biological and chemical sensors capable of highly sensitive detection of various entities and processes. While significant progress has been made towards improving their sensitivity, much is yet to be explored in the study of various critical parameters, such as the choice of a se...

Poly-SiGe is investigated as the gate material for CMOS transistors with ultra-thin Hf02 gate dielectric. Compared with polySi, poly-SiGe reduces the gate depletion effect, and also results in thinner EOT of the gate dielectric after 1000°C annealing, with low gate leakage maintained. The Si interface quality is also better than that achieved with surface nitridation, which has been used to red...

Ultra-low effective oxide thickness (EOT) Ge MOS devices with different HfON/HfAlO stacks and sintering temperatures were investigated in this work. Both the reduced gate leakage current and reliability improvement can be achieved by either a suitable gate dielectric stack or sintering temperature. As a whole, a 0.5 nm thick HfAlO in gate dielectric stack and a sintering temperature at 350 C ar...

In this study, we present selected reliability issues of double gate dielectric stacks for non-volatile semiconductor memory (NVSM) applications. Fabricated gate structures were consisted of PECVD silicon oxynitride layer (SiOxNy) as the pedestal layer and hafnium dioxide layer (HfO2) as the top gate dielectric. In the course of this work, obtained MIS structures were investigated by means of c...

We designed acene molecules attached to two semi-infinite metallic electrodes to explore the source-drain current of graphene and the gate leakage current of the gate dielectric material in the field-effect transistors (FETs) device using the first-principles density functional theory combined with the non-equilibrium Green's function formalism. In the acene-based molecular junctions, we modify...

Dual-metal gate CMOS devices with rapid-thermal chemicalvapor deposited (RTCVD) Si3N4 gate dielectric were fabricated using a self-aligned process. The gate electrodes are Ti and MO for the Nand PMOSFET respectively. Carrier mobilities are comparable to that predicted by the universal mobility model for Si02. C-V characteristics show good agreement with a simulation that takes quantum-mechanica...