The design of a I-input and a ?-input 4-valued logic gate is described. These gatcs can be used to implement cells of a gate array, with the benefit of having prograrnriiabk functionality and multiple-valued logic input and output lincs. Programmable fimctionality allows any or the four billion functions of a '-input 4-valued logic gate to be implemented by thc samc cell, and multiplc-valucd hg...

Demand for high-speed dynamic reconfiguration of a programmable device is increasing for raising the performance level of such devices. To support high-speed dynamic reconfiguration, optically reconfigurable gate arrays (ORGAs) have been developed. An ORGA consists of a holographic memory, a laser array, and an optically reconfigurable gate array VLSI. The holographic memory can store many conf...

Achieving small transverse beam emittance is important for high brightness cathodes for free electron lasers and electron diffraction and imaging experiments. Double-gate field emitter arrays with on-chip focussing electrode, operating with electrical switching or near infrared laser excitation, have been studied as cathodes that are competitive with photocathodes excited by ultraviolet lasers,...

Gate-arrays are the most common design style for semicus-tom VLSI integrated circuits. An important part of the gate-array design process is the routing of wires between the logic elements, which is an extremely compute-intensive operation. This paper presents an algorithm for routing gate-arrays that uses a hypercube connected parallel processor to provide the necessary computation power. In o...

As intended by its name, Physically Unclonable Functions (PUFs) are considered as an ultimate solution to deal with insecure storage, hardware counterfeiting, and many other security problems. However, many different successful attacks have already revealed vulnerabilities of certain digital intrinsic PUFs. This paper demonstrates that legacy arbiter PUF and its popular extended versions (i.e.,...

The paper proposes mvTANTs , three-level networks with multiple-valued inputs and binary outputs. These networks are a generalization of binary T A N T s (Three level And Not networks with True Inputs). One of possible interpretations of m v T A N T is a four-level binary network with input decoders which realize multiplevalued literals. Similarly to mvPLAs, mvTANTs have regular structures with...