In this paper, a novel gate technology with triple shaped gate structure has proposed and developed in order to suppress unwanted gate fringing capacitance. Because high gate stem height was difficult to fabricate by means of conventional direct electron beam (E-Beam) lithography method, additional PMGI sacrificial layer was utilized in this new scheme. Increasing gate stem height as an amount ...

Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such that the delay of a combinational circuit is minimized while the cost constraint is satisfied. It is one of the most studied problems in VLSI computer-aided design. Despite this, all of the existing techniques are heuri...

In this Letter, we report gate-tunable X-ray photoelectron emission from back-gated graphene transistors. The back-gated transistor geometry allows us to study photoemission from graphene layer and the dielectric substrate at various gate voltages. Application of gate voltage electrostatically dopes graphene and shifts the binding energy of photoelectrons in various ways depending on the origin...

In the present paper we have done a comparative analysis of Dual Gate MOSFET having split gate architecture and conventional Dual Gate MOSFET architecture. Simulations have been performed using SILVACO-ATLAS tool, which shows significant improvement in characteristic of split gate architecture in comparison to the conventional structure. The split gate architecture consist two different materia...

This paper presents a way to enhance the Differential Current-Switch Threshold Logic gate (DCSTL) in order to allow the gate to perform more complex functions. This enhancement is achieved by replacing the MOS-transistors at the dataand threshold mapping bank of the DCSTL gate with neuronMOS transisors. First, we introduce the neuronMOS-enhanced DCSTL gate. Then, the results of HSPICE simulatio...

---In this paper a thorough investigation of resistive logic RCJL gate has been made. The current equations of this gate at each stage have been deduced. The dynamic response of this gate has been obtained by the computer-simulation. Our concept of turn-on delay has been introduced. The effect of overdrive current on turn-on delay for resistive logic gate has been shown. This will provide a bet...

Degradation phenomena due to hot carrier stress conditions were investigated in double-gate polysilicon thin film transistors fabricated by sequential lateral solidification (SLS). We varied the hot carrier stress conditions at the front gate channel by applying various voltages at the back-gate. Thus, we investigated the device electrical performance under such stress regimes. As a conclusion,...

Gate and drain current noise investigations are performed on nMOS transistors with HfO2 gate oxides. The drain noise magnitude allows extraction of the slow oxide trap density Nt(EF) ranging from 3 to 7 10 eV cm. These values are about 50 times higher than for SiO2 dielectrics. The 1/f gate current noise component is a quadratic function of the gate leakage current. The gate noise parameter KGC...